FR2912854A1 - Packet receiving device for e.g. Internet Protocol type packet-switched communication network, has generating unit for generating zero crossing of meter, and reconstituting unit for reconstituting synchronizing signal based on image cues - Google Patents

Abstract

The device has a regenerating unit for regenerating a counting ramp e.g. program clock reference counter, using a phase-lock loop (PLL-1) which receives local samples (PCR-LOC-n-1). An initializing unit initializes an image meter clocked by a reconstituted clock (CLK-out-n), and a generating unit generates zero crossing of the meter from image cues. A reconstituting unit reconstitutes a genlock type synchronizing signal based on the cues, and a base of synchronized time on all stations of a network is confirmed to international electro technical commission (IEC 61588) standard.

Description

1 REDUCTION OF A TRIGGER OF A SYNCHRONIZATION SIGNAL IN A NETWORK

  PACKET SWITCHING Field of the invention

  The present invention relates to the field of video equipment. The present invention relates more particularly to a device for receiving a synchronization signal on a packet-switched communication network, for example of the IP 10 type (acronym for the English expression Internet Protocol), that the network is wired (for example, Ethernet (IEEE802.3)) or non-wired, (for example, IEEE 802.16 D-2004). State of the art

  Advances in the ability of IP networks to carry any type of signal (data or video) make it possible to use such networks as a backbone architecture for video studios. A major interest of this evolution is to then have a unique infrastructure for data transport. Whereas in the past, several media were needed to carry different types of signals between the equipments, the multiplexing properties offered by the IP layer make it possible to reduce to one the number of necessary media: an IP network which connects the different equipments.

  In the state of the art, the synchronization of video equipment (cameras, etc.) in a studio is achieved by the transmission of a synchronization signal commonly called Genlock or black burst. For example, the Genlock signal is composed of two synchronization signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 s (for a standard format and less for an HD format) and indicates the beginning of the lines in the video frame. The waveforms of the synchronization signals are a function of the format of the image transmitted on the network. For example, for a high-definition image, the synchronization signal has a shape called tri-level (-300mV, OV, +300 mV).

  When a synchronization signal is routed to various equipment to be synchronized by a dedicated coaxial cable, it is ensured a constant transmission time without jitter (phenomenon called jitter in English). From such a signal, any equipment is able to reconstruct a timing clock specific to its operation that ensures that its operation is strictly in phase with all equipment connected to the same network. For example, two cameras synchronized by a Genlock signal traveling on a dedicated coaxial cable, each generate a video of a different content but rigorously in frequency and phase relative to each other.

  A known disadvantage presented by an IP / Ethernet network comes from the fact that it introduces a strong jitter in a signal transmission and in particular for the transmission of a synchronization signal. When such a signal is routed over an IP / Ethernet link to various equipment to be synchronized, this jitter results in temporal fluctuations in the duration with which the information carried by the synchronization signal reaches the equipment.

  In the prior art, there are known devices for reconstructing at each camera, a clock clock specific to this camera to overcome the jitter. The principle of these devices is based on a strong attenuation of the jitter amplitude of the synchronization signal at the reception. It can thus be guaranteed that an image generated by a camera is strictly in phase with all the images generated by the neighboring cameras connected to the same network. Examples of such jitter attenuation devices are described in PCT international application FR2007 / 050918, they act on so-called digital counter signals (or PCR which is the acronym for the English expression Program Clock Reference) , which are representative of very precise reference clock signals. These digital signals are provided to cameras through a network so that they can locally reconstruct clock signals in phase with the reference clock.

  The transmission device according to the prior art comprises means for: extracting image tops from a synchronization signal; -Initialize a first counter from image tops; - Initialize a second counter every 25 m zero crossings of the first counter; -Sampling the second counter CSE_PCR1 all periods Teh, where Teh is derived from a synchronized time base on all stations of said network; - Send packets containing the 30 samples in the network.

  The receiving device according to the prior art comprises means for: - receiving packets containing network samples from sampled data all periods Teh; 4 - regenerating a first counter CSR_PCR1 using a phase locked loop PLL1; initializing a second counter CPT all the zero crossings of said first counter CSR_PCR1; generating all the zero crossings of said second counter CPT; and - reconstituting a synchronization signal from said image tops. The PLL1 phase lock loop (PLL) of the receiving device behaves as a second-order low-pass filter which partially attenuates the jitter present on the samples carried. on the network.

  However, in certain situations, for example when the jitter has a very high amplitude, the attenuation achieved using the PLL1 phase-locked loop is not always sufficient: the residual jitter is too great for the signal synchronized synchronization allows to synchronize the equipment that includes the receiving device.

  The problem consists in transmitting a top image to a remote device through an IP / Ethernet network, the top image received by the remote equipment remaining strictly in phase with the top transmitted image. This amounts to finding a means for generating on a remote device connected to an IP network, introducing a jitter, a video clock and an image synchronization top. These two signals make it possible to regenerate a Genlock signal strictly in phase with a reference genlock signal. SUMMARY OF THE INVENTION

  The technical problem that the present invention proposes to solve is the transmission of a synchronization signal through a packet switched network with a non-constant transmission duration.

  For this purpose, the present invention relates to a reception device able to receive packets in a packet communication network comprising at least two stations, said device comprising means for: receiving packets containing samples of said network, said samples coming from sampled data for all Tech periods, where Tech is from a synchronized time base on all stations in that network; regenerating a counting ramp CSR_PCR1 by means of a PLL1 phase locked loop receiving the samples and delivering in addition local samples PCR_locl all the Tech periods and a reconstituted clock CLK_outl; characterized in that it comprises, for n which is an integer strictly greater than 1, and for i which is an index comprised between 2 and n, means for: -regenerate a counting ramp CSR_PCRi with the aid of a phase locked loop PLL1 which receives local samples PCR_loci_1 and which delivers, in addition, local samples PCR_loci all Tech periods and a reconstituted clock CLK_outr; - Initialize, at all zero crossings of the counting ramp CSR_PCRn, a picture counter CPT which is clocked by the reconstituted clock CLK_outn ,; generating all the zero crossings of said image counter CPT; and 6 -reconstitute a synchronization signal from said image tops.

  Preferably, the synchronization signal 5 is of Genlock type. According to one embodiment, the counting ramps CSR_PCR are PCR counters (acronym for the English expression Program Clock Reference). According to a particular mode of implementation, the synchronized time base on all the stations of the network is in the IEC 61588 standard.

  A first advantage of the invention lies in the capacity it offers to attenuate the jitter of a synchronization signal conveyed through a non-constant transmission time-switched packet network with a factor much greater than that attenuation performed by a receiving device according to the prior art. This advantage is particularly suitable for attenuating a very high amplitude jitter, for example, to reconstruct a synchronization signal having circulated on an Ethernet network in a situation of momentary overload. A second advantage of the invention lies in the simplicity of its production and development. It is known that a PLL1 phase-locked loop can be designed from VHDL (English acronym for Very High Speed Integrated Circuit Hardware Description Language) codes. A design of a receiving device having a plurality of cascaded PLL phase locked loops represents a complexity which is not substantially greater than that of a device which has a single PLL loop since this cascade can result in a duplication of parts of VHDL code. For the same reason, the debugging and testing times of a cascade of PLL loops are substantially equal to the debugging and testing times of a single PLL loop. Brief description of the drawings

  The invention will be better understood by means of the description, given below for purely explanatory purposes, of one embodiment of the invention, with reference to the appended figures: FIG. 1 illustrates the transmission of a Genlock information between two cameras connected by an IP / Ethernet network; - Figure 2 illustrates the interfacing between an analog domain and an IP / Ethernet network; 3 represents the sampling of the PCR counter by Teh; FIG. 4 illustrates the regeneration of the Genlock signal on the reception side according to the prior art; FIG. 5 illustrates the operation of a phase-locked loop used on the reception side according to the prior art; Figure 6 illustrates the generation of the Genlock signal on the receiving side according to the invention; FIG. 7 represents counting ramps and image counting ramps on the transmission side and the receiving side side. DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

  The current analog world is interfaced to the IP / Ethernet network on the sending side, and the IP / Ethernet network is interfaced to the receiving-side analogue world, as shown in Figure 1. In this same figure, the transmission side consists of a Genlock Master (or Genlock master) MGE that is connected to an Analog / IP I AIP interface. 8 The Genlock Master MGE generates a Genlock SGO signal for I AIP interfaces. The reception side consists of two cameras (CAM1, CAM2) each connected to an IP / Analog I IPA interface. The IPA interfaces I which will ultimately be included in the cameras themselves are responsible for reconstructing Genlock SG1, SG2 signals for cameras CAM1, CAM2. The cameras CAM1, CAM2 each produce a video signal SV1, SV2 which one wishes to synchronize perfectly. The transmitting and receiving sides are interconnected by a packet-switched network which causes jitter appearing on the Genlock SGO signal.

  A sampling top, at the period Teh, is generated from a first synchronization layer, for example IEEE1588, is addressed to the transmission and reception sides. Indeed, the PTP protocol (acronym for Precision Time Protocol) based on IEEE1588 makes it possible to obtain synchronization between the devices connected on an Ethernet network of the order of one microsecond. In other words, all the time bases of each device evolve at the same time to an accuracy close to the microsecond. These timebases can be used in this case to generate each their own sample at the Teh period. The use of the IEEE1588 layer is not a must. Any system for providing sample rates at the Teh period on the different devices connected on a network may be suitable. For example, it is possible to use a 5ms period sampling peak derived from a wireless transmission physical layer. In FIG. 2, the processing of the Genlock SGO signal originating from MGE, within the interface I, is detailed. AIP. First, an EXS module extracts timing information from the SGO signal to retrieve a timing video clock (denoted Clk video in Figure 2). More precisely, the EXS module is in charge of generating a top image at each image start. In addition, the EXS module comprises an image counter, for example a 40 msec counter, which is not shown in FIG. 2. The output of this image counter changes according to a counting ramp passing through 0 at each image period, that is to say every 40 ms if we consider the image counter cited above as an example.

  The video timing clock is used to clock a CPT_PCR counter. The output of the CPT PCR counter is a counting ramp CSE PCR, whose period is worth m image periods. All images, the counter CPT_PCR is reset, that is to say that the counting ramp CSE PCR is reset to 0. Subsequently, a LCH module samples the counting ramp CSE_PCR is all periods Teh to produce PCRe samples. These PCR samples are sent over the network and flow to the receiving side through a network interface (INTE block).

  Figure 3 shows the sampling of the counter CPT_PCR at the period Teh.

  Figure 4 shows the receiving side according to the prior art. The IPA I interface retrieves PCRe samples sent over the network to reconstruct the Genlock signal locally. These PCR samples are received through a network interface (INTR module). The INTR module produces representative PCR samples in PCRe samples. These PCR samples, which have been produced at regular intervals on the transmission side, arrive at irregular intervals on the reception side: this is due mainly to the jitter introduced during transport on the network. The PCR in samples are taken into account at regular intervals Teh and because of this, most of the jitter introduced during the transport of packets is eliminated.

  The inaccuracy between the sampling times of transmission and reception is absorbed by a PLL1 phase-locked loop whose bandwidth is appropriate. The characteristics of the PLL1 loop guarantee CLK_outl reconstituted clock generation with reduced jitter. The phase locked loop PLL1 behaves as a system receiving PCR in samples and delivering: - a reconstituted clock CLK_out1, - a counting ramp CSR_PCR1 and - local samples PCR_loc1. When the PLL1 loop is operating in steady state, the PCR in samples are substantially equal to the PCR loc1 samples.

  The reconstituted clock CLK_outl runs a CPT image counter similar to the emission-side image counter, for example a 40 ms counter. The image counter CPT is reset at each passage of the count ramp CSR_PCR1 by 0. Between two successive initializations, the image counter CPT evolves freely and produces a top image which feeds a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1, SG2 intended to synchronize the CAM1, CAM2 cameras. The reconstructed genlock signal SG1, SG2, which is generated from the counting ramp CSR_PCR1 and the reconstituted clock CLK_outl is in phase with the Genlock signal SGO on the sending side, at clock stroke 11. The PLL1 loop provides filtering that can be modeled as a 2nd order low pass filter.

  Figure 5 illustrates a mode of operation of a PLL1 phase locked loop employed in an IPA interface. As represented in FIG. 5, the phase-locked loop PLL1 comprises: a CORCMPI corrector / comparator which receives the PCR_in samples as well as the local PCR loc1 samples. CORCMPI delivers a comparison result of the samples; a digital oscillator VCO1 which is controlled by a sample comparison result and which delivers a reconstituted clock CLK_outl; a counter CPT_PCR1 producing a counting ramp CSR_PCR1 according to a rate printed by the reconstituted clock CLK_out1; a LATCHI value maintenance system, which generates local samples PCR_locl from the values of the counting ramp CSR_PCR1 at times Teh;

  The problem of rigorous rate recovery in a high amplitude jitter situation is solved by attenuating the jitter with a factor greater than that allowed by the PLL1 phase locked loop. This higher jitter attenuation factor is achieved by cascading at least two phase lock loops similar to that described in FIG. 5. The major constraint for this to be achievable is that the sampling times of the CPT PCR counter, on transmission and those setting the sampling performed within the phase lock loops of the receiving device are identical. The technical problem for those skilled in the art is that of receiving a synchronization signal through an IP / Ethernet network which introduces a strong jitter rigorously in phase with the transmission. From the moment this is feasible, the construction of the Genlock signal is then possible.

  Figure 6 illustrates the reception of the Genlock signal according to the invention. The IP / analog IPA interface comprises a total number of PLLk phase-locked loops, where n is an integer strictly greater than 1 and where k is an index between 1 and n. The n PLLk phase lock loops are similar to that shown in FIG. 5. According to the invention, the PLL1 loop receives PCR samples that have circulated on the Ethernet network. The loop PLL1 produces a reconstituted clock CLK_out1, a counting ramp CSR_PCR1 and local samples PCR_locl Moreover, each PLL loop, for i which is an integer between 2 and n, receives local samples PCR_loci_1 and delivers: - a reconstructed clock CLK_outr, - a counting ramp CSR_PCR and - local samples PCR loc, _ 1 are obtained from a sampling of the counting ramp CSR_PCR at times Teh. A CPT image counter, clocked by the reconstituted clock CLKout, produces a top image. The image counter CPT is similar to the image counter used on the transmission side, it is for example a counter at 40 ms. In addition, the image counter CPT is reset each time each change to 0 of the counting ramp CSR_PCRn. A receiving device according to the invention which comprises n identical PLLk phase-locked loops provides a filtering which can be modeled as a 2n-order low-pass filter. Each PLLk phase-locked loop may have filtering and response characteristics that are independent of one another. This allows, if necessary, to set a filter mask.

  Figure 7 illustrates the transmission of potential top-picture information. On the emission side: from the Genlock SGO signal, image tops are extracted. From the image tops, for example of recurrence 40 ms, the transmission image counter is initialized. Every m zero crossings of the emission image counter, the counter CPT PCR is initialized: that is to say that the output ramp CSE PCR produced by the counter CPT_PCR is periodically zeroed. A sampling of the output ramp CSE_PCR, at a rate Teh provided by the network, produces PCR samples that are sent over the network. Receiving side: the counting ramp CSRPCR is regenerated in phase with the counting ramp CSE PCR by the last phase locked loop PLLn of the phase locked loop cascade. At the zero crossing of the ramp CSR_PCRn, the reception image counter CPT is initialized, which then evolves freely. The latter will necessarily remain synchronous counter CPT_PCRn since they both use the same reconstituted clock CLK_outn. The zero crossing of the output of the reception image counter CPT makes it possible to generate the reception top image. From this reception top image, it is possible to reconstruct with the Genlock signal SG1, SG2 on the reception side.

  Since the counting ramps CSE_PCR and CSRPCR are strictly synchronous with each other, the image counters (counter at 40 ms) on the sending and receiving side are also synchronous and therefore the transmit and receive image tops are necessarily in phase.

  In addition, the top image on the receiving side has no jitter compared to the video clock on the receiving side.

The invention is described in the foregoing by way of example. It is understood that the skilled person is able to realize different variants of the invention without departing from the scope of the patent.

Claims (4)

  A reception device capable of receiving packets in a packet communication network comprising at least two stations, said device comprising means for: receiving packets containing samples of said network, said samples coming from data sampled all the periods Teh where Teh is from a synchronized time base on all stations of said network; regenerating a CSRPCR counting ramp by means of a PLL1 phase-locked loop receiving the samples and delivering in addition local samples PCR_locl all the periods Teh and a reconstituted clock CLK_outl; characterized in that it comprises, for n which is an integer strictly greater than 1, and for i which is an index between 2 and n, means for: - regenerating a counting ramp CSR_PCR with the aid of a PLL phase locked loop which receives local samples PCR_loci_1 and which delivers, in addition, local samples PCR_loc all periods Teh and a reconstituted clock CLK_out1; initializing, at all the zero crossings of the counting ramp CSR_PCRn, a picture counter CPT which is clocked by the reconstituted clock CLKout; generating all the zero crossings of said image counter CPT; and - reconstituting a synchronization signal from said image.35 tops 16   2. Receiving device according to claim 1, characterized in that the synchronization signal is Genlock type.   3. receiving device according to one of claims 1 or 2, characterized in that the counting ramps CSR_PCR, are PCR counters.   4. Receiving device according to any one of claims 1 to 3, characterized in that the synchronized time base on all stations of the network is IEC 61588 standard.