FR2893159B1 - Procede et dispositif pour l'analyse de circuits integres - Google Patents

Procede et dispositif pour l'analyse de circuits integres

Info

Publication number
FR2893159B1
FR2893159B1 FR0553354A FR0553354A FR2893159B1 FR 2893159 B1 FR2893159 B1 FR 2893159B1 FR 0553354 A FR0553354 A FR 0553354A FR 0553354 A FR0553354 A FR 0553354A FR 2893159 B1 FR2893159 B1 FR 2893159B1
Authority
FR
France
Prior art keywords
integrated circuits
analyzing integrated
analyzing
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0553354A
Other languages
English (en)
Other versions
FR2893159A1 (fr
Inventor
Stephane Guedon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Edxact SA
Original Assignee
Edxact SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Edxact SA filed Critical Edxact SA
Priority to FR0553354A priority Critical patent/FR2893159B1/fr
Priority to US11/795,511 priority patent/US8165861B2/en
Priority to PCT/EP2006/068074 priority patent/WO2007051838A1/fr
Publication of FR2893159A1 publication Critical patent/FR2893159A1/fr
Application granted granted Critical
Publication of FR2893159B1 publication Critical patent/FR2893159B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
FR0553354A 2005-11-04 2005-11-04 Procede et dispositif pour l'analyse de circuits integres Active FR2893159B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0553354A FR2893159B1 (fr) 2005-11-04 2005-11-04 Procede et dispositif pour l'analyse de circuits integres
US11/795,511 US8165861B2 (en) 2005-11-04 2006-11-03 Printed circuit analysis method and device
PCT/EP2006/068074 WO2007051838A1 (fr) 2005-11-04 2006-11-03 Procede et dispositif pour l'analyse de circuits integres

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0553354A FR2893159B1 (fr) 2005-11-04 2005-11-04 Procede et dispositif pour l'analyse de circuits integres

Publications (2)

Publication Number Publication Date
FR2893159A1 FR2893159A1 (fr) 2007-05-11
FR2893159B1 true FR2893159B1 (fr) 2013-02-08

Family

ID=36717003

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0553354A Active FR2893159B1 (fr) 2005-11-04 2005-11-04 Procede et dispositif pour l'analyse de circuits integres

Country Status (3)

Country Link
US (1) US8165861B2 (fr)
FR (1) FR2893159B1 (fr)
WO (1) WO2007051838A1 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8091052B2 (en) * 2007-10-31 2012-01-03 Synopsys, Inc. Optimization of post-layout arrays of cells for accelerated transistor level simulation
FR2931971B1 (fr) 2008-06-03 2010-08-13 Edxact Filtrage de petites valeurs pour la verification des circuits integres
FR2933515B1 (fr) 2008-07-04 2017-03-31 Edxact Systeme pour calcul des valeurs resistives pour la cao micro electronique
FR2944897B1 (fr) 2009-04-24 2016-01-22 Docea Power Procede et dispositif pour la creation et l'exploitation des modeles thermiques.
US8762912B2 (en) * 2009-10-30 2014-06-24 Synopsys, Inc. Tiered schematic-driven layout synchronization in electronic design automation
US8245169B2 (en) 2009-12-29 2012-08-14 International Business Machines Corporation Generating capacitance look-up tables for wiring patterns in the presence of metal fills
US8782577B2 (en) 2010-07-24 2014-07-15 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
WO2012018571A1 (fr) * 2010-07-24 2012-02-09 Cadence Design Systems, Inc. Procédés, systèmes et articles de fabrication destinés à mettre en application des conceptions de circuit électronique avec une prise de conscience d'électromigration
US8689169B2 (en) 2010-07-24 2014-04-01 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
US8640076B2 (en) 2010-10-18 2014-01-28 International Business Machines Corporation Methodology on developing metal fill as library device and design structure
US8418112B2 (en) 2011-03-03 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating RC technology file
US9542515B2 (en) * 2011-11-28 2017-01-10 Cadence Design Systems, Inc. Methods, systems, and computer-readable media for model order reduction in electromagnetic simulation and modeling
US9640994B2 (en) * 2012-02-24 2017-05-02 Mitsubishi Electric Research Laboratories, Inc. Decoupled three-phase power flow analysis method for unbalanced power distribution systems
EP2701478A1 (fr) * 2012-08-20 2014-02-26 Siemens Aktiengesellschaft Bloc destiné à un appareil dýautomatisation modulaire
US10402532B1 (en) * 2016-04-07 2019-09-03 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components
US11501049B1 (en) * 2018-09-28 2022-11-15 Cadence Design Systems, Inc. Systems and methods for modeling interactions of power and signals in a multi-layered electronic structure
US11960808B1 (en) * 2021-09-02 2024-04-16 The United States of America, as represented by Secretary of the Navy Computer-implemented method for deriving resistance, inductance, and capacitive (RLC) values of an RLC equivalent circuit model associated with a fireset

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR553354A (fr) 1922-06-26 1923-05-23 Perfectionnements apportés dans l'établissement des carrosseries plus spécialement applicables aux véhicules automobiles
GB2274372A (en) * 1992-12-02 1994-07-20 Ibm Adaptive noise cancellation device
JP3670553B2 (ja) * 2000-03-27 2005-07-13 株式会社東芝 半導体集積回路解析装置、半導体集積回路解析方法及び半導体集積回路解析方法を実行するためのプログラムを記録した記録媒体
JP3971167B2 (ja) * 2001-11-20 2007-09-05 株式会社ルネサステクノロジ 等価回路の導出方法、および、そのためのシステム
US7496871B2 (en) * 2003-10-21 2009-02-24 Roberto Suaya Mutual inductance extraction using dipole approximations
US7774174B2 (en) * 2004-04-07 2010-08-10 Mentor Graphics Corporation Branch merge reduction of RLCM networks
US7277804B2 (en) * 2004-06-29 2007-10-02 Cadence Design Systems, Inc. Method and system for performing effective resistance calculation for a network of resistors
US7228259B2 (en) * 2004-06-30 2007-06-05 Lucent Technologies Inc. Method and apparatus for structure-preserving reduced-order modeling
US7315212B2 (en) * 2005-04-13 2008-01-01 International Business Machines Corporation Circuits and methods for implementing transformer-coupled amplifiers at millimeter wave frequencies
US20070005325A1 (en) * 2005-06-30 2007-01-04 Jian Gong Circuit simulation using precision-space concept
EP1907956B1 (fr) * 2005-07-26 2012-12-26 Mentor Graphics Corporation Simulation analogique et/ou rf acceleree
FR2933515B1 (fr) * 2008-07-04 2017-03-31 Edxact Systeme pour calcul des valeurs resistives pour la cao micro electronique

Also Published As

Publication number Publication date
FR2893159A1 (fr) 2007-05-11
US8165861B2 (en) 2012-04-24
WO2007051838A1 (fr) 2007-05-10
US20080133201A1 (en) 2008-06-05

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