WO2012018571A1 - Procédés, systèmes et articles de fabrication destinés à mettre en application des conceptions de circuit électronique avec une prise de conscience d'électromigration - Google Patents

Procédés, systèmes et articles de fabrication destinés à mettre en application des conceptions de circuit électronique avec une prise de conscience d'électromigration Download PDF

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Publication number
WO2012018571A1
WO2012018571A1 PCT/US2011/045104 US2011045104W WO2012018571A1 WO 2012018571 A1 WO2012018571 A1 WO 2012018571A1 US 2011045104 W US2011045104 W US 2011045104W WO 2012018571 A1 WO2012018571 A1 WO 2012018571A1
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Prior art keywords
electrical
electro
implemented method
computer implemented
electronic circuit
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PCT/US2011/045104
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English (en)
Inventor
David White
Michael Mcsherry
Ed Fischer
Bruce Yanagida
Prakash Gopalakrishnan
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Cadence Design Systems, Inc.
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Priority claimed from US12/982,762 external-priority patent/US9330222B2/en
Application filed by Cadence Design Systems, Inc. filed Critical Cadence Design Systems, Inc.
Publication of WO2012018571A1 publication Critical patent/WO2012018571A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Definitions

  • VDSM very deep sub-micron
  • the present invention presents methods, systems, and computer program products for implementing a method for implementing an electronic circuit design with electro-migration awareness.
  • the invention allows for electronic circuit designs with electro-migration awareness early in the design stage.
  • identifying, determining, or updating physical data of a component of a partial physical design of the electronic circuit design characterizing an electrical parasitic that is associated with the physical data of the component; and characterizing an electrical characteristic that is associated with the electrical parasitic and the physical data.
  • process further comprises displaying the electrical characteristic associated with the physical data of the component or storing the electrical characteristic in a non- transitory computer readable storage medium.
  • the process further comprises identifying or determining an electro-migration related constraint that is associated with the electrical characteristic.
  • the act of identifying or determining the electro-migration related constraint may include determining whether the electrical characteristic or other data related to the electro-migration related constraint meets a requirement of the electro-migration related constraint for the component.
  • the electro-migration related constraint may be determined based at least in part upon a shape or a set of shapes on a net at a time when the net is created or completed.
  • process further comprises ensuring correctness of the physical data or other data that are related to the electro-migration related constraint.
  • the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises performing simulation on the electronic circuit design at a schematic level, creating a net on the layout, and determining the electrical characteristic by using a solver.
  • the act of using the solver may include using at least the electrical parasitic to construct a matrix, decomposing the matrix into an upper triangular matrix and a lower triangular matrix, using forward and backward substitution to solve for a second electrical characteristic and characterizing the electrical characteristic for the component by using at least the second electrical characteristic.
  • the matrix may include an electrical conductance matrix and the second characteristic may include a voltage at a point in the partial physical design.
  • the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises identifying or generating thermal data and a schematic of the electronic circuit design, generating a netlist, specifying one or more simulation parameters or one or more analysis points or corners, performing a simulation at a schematic level to determine one or more schematic level electrical characteristics, and determining the electrical characteristic at a physical level based at least in part upon the one or more schematic level electrical characteristic and the electrical parasitic using a solver.
  • process further comprises identifying or determining an electro-migration related constraint that is associated with the electrical characteristic wherein the act of identifying or determining the electro-migration related constraint includes
  • the component determining whether the electrical characteristic or other data related to the electro- migration related constraint meets a requirement of the electro-migration related constraint for the component; identifying or determining one or more relevant geometric parameters related to the component; and identifying or determining whether to analyze the component using the electro-migration related constraint based at least in part upon the one or more relevant geometric parameters.
  • process further comprises determining an adjustment to the physical data or to the component based at least in part upon the electro-migration related constraint.
  • the process further comprises determining an adjustment to the physical data or to the component based at least in part upon the electro-migration related constraint and determining whether the adjustment causes one or more violations of one or more design rules or one or more constraints.
  • Additional objectives and advantages may be realized when the process further comprises determining an adjustment to the physical data or to the component based at least in part upon the electro-migration related constraint and displaying a hint based at least in part upon the adjustment to a user.
  • the hint may be generated for application of the adjustment or for fixing the one or more violations.
  • Additional objectives and advantages may be realized when the partial physical design does not pass a layout versus schematic check or verification.
  • Additional objectives and advantages may be realized when the act of characterizing an electrical parasitic or the act of characterizing the electrical characteristic is performed at a time of creation of a net or modification of an existing net.
  • the act of characterizing the electrical parasitic may be done before storing one or more shapes that are created or modified and constitute the net in a database.
  • Additional objectives and advantages may be realized when implementing an electronic circuit design with electro-migration awareness further comprises verifying the electrical characteristic after completion of creation or modification of a net or a partial net and before creation or modification of a second net in the partial physical design.
  • the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises performing simulation on the electronic circuit design at a schematic level, creating a net on the layout, and determining the electrical characteristic by using a solver; wherein the act of using the solver may include using at least the electrical parasitic to construct a matrix, decomposing the matrix into an upper triangular matrix and a lower triangular matrix, using forward and backward substitution to solve for a second electrical characteristic and
  • the matrix may include an electrical conductance matrix and the second characteristic may include a voltage at a point in the partial physical design; and where the electrical characteristic comprises at least one of a maximum current and an RMS current.
  • implementing an electronic circuit design with electro-migration awareness involves performing a process that comprises identifying, determining, or updating physical data of a component of a partial physical design of the electronic circuit design; characterizing an electrical parasitic that is associated with the physical data of the component; characterizing an electrical characteristic that is associated with the electrical parasitic and the physical data; and using the electrical characterization to specify, create, or modify an interconnect shape or net as part of routing.
  • the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises performing simulation of the electronic circuit design at a schematic level, creating a net on the layout, and determining the electrical characteristic using a solver.
  • Additional objectives and advantages may be realized where the partial physical design comprises only one or more nets and does not pass a layout versus schematic check or verification. [0028] Additional objectives and advantages may be realized where the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed before creation of a net.
  • Additional objectives and advantages may be realized when implementing an electronic circuit design with electro-migration awareness further comprises verifying the electrical characteristic after completion of creation or modification of a net or a partial net and before creation or modification of a second net in the partial physical design.
  • FIGs. 1 A-B illustrate top level block diagrams for implementing various embodiments of the methods or systems for implementing electronic circuit design with electro-migration awareness.
  • Figs. 2A-H and J illustrate more detailed block diagrams for the method or system for implementing electronic circuit design with electro-migration awareness and some detailed information about the process or module for characterizing one or more electrical characteristics that are associated with electrical parasitics in some embodiments.
  • Figs. 3A-B illustrate more details for the process or module for characterizing one or more electrical characteristics that are associated with one or more electrical parasitics in some embodiments.
  • Fig. 4 illustrates more details for the process or module for characterizing one or more electrical parasitics associated with the physical data and for characterizing one or more electrical characteristics that are associated with one or more electrical parasitics in some embodiments.
  • Fig. 5 illustrates more details for the process or module for characterizing one or more electrical parasitics associated with the physical data and for characterizing one or more electrical characteristics that are associated with one or more electrical parasitics in some embodiments.
  • Fig. 6 illustrates more details for the process or module for implementing electronic circuit design with electro-migration awareness in some embodiments.
  • Fig. 7 illustrates a more detailed flow diagram for the method or system for implementing electronic circuit designs with electro-migration awareness.
  • Fig. 8 illustrates a more detailed flow diagram for the method or system for implementing electronic circuit designs with electro-migration awareness.
  • Fig. 1 A which illustrates a top level diagram for implementing various embodiments of the methods or systems for implementing electronic circuit design with electro-migration awareness
  • the method or system for implementing electronic circuit designs with electro-migration awareness comprises the process or module for identifying, determining, or updating physical data of a net, a device, or a component (hereinafter "a component" collectively) of an electronic circuit physical design (102) in various embodiments.
  • implementing electronic circuit designs with electro-migration awareness may further comprise the process or hardware module for characterizing one or more electrical parasitics that are associated with physical data at 104.
  • the method or system for implementing electronic circuit designs with electro-migration awareness may comprise the process or hardware module for characterizing the electrical characteristics that are associated with the one or more electrical parasitics and the physical data at 106.
  • a user may invoke or utilize the methods or the systems described herein via a terminal or a user interface 1 10.
  • the method or the system needs only a partial layout that comprises merely one component, such as an interconnect wire segment, a via, or a via cluster, to perform its intended functions of implementing electronic circuit design with electro-migration awareness.
  • some embodiments as described herein do not require a complete physical layout that have gone through the complete placement, global routing, and detail routing stages. That is, the method and system provide the designers with the ability to implement the electronic circuit design with electro-migration awareness from the first
  • interconnect segment meets one or more EM related constraints and whether and what kind of adjustments need to be made to the design to ensure the compliance of the one or more EM related constraints.
  • the action of determining whether the segment meets the EM related constraints and subsequent adjustment(s) occurs before one or more subsequent physical design objects are created.
  • the act of determining is done before the created or modified physical design object is stored in a database.
  • an adjustment comprises creation of a new route or a segment thereof or modification of an existing route or a segment thereof.
  • an adjustment comprises placement of a component in a physical design of an electronic circuit design.
  • the characterization of electrical parasitics associated with physical data may be done with a two stage approach. This process begins with the selection a particular net or partial net. In the first stage, the process identifies where along that net that a geometric description should be created.
  • the geometric descriptions may include wire widths and spacings, conductor and ILD (inter layer dielectrics) thicknesses, or thickness of barrier materials.
  • a common description may be created and provided via an API (application programming interface.)
  • the second stage may include one or more components that may translate, transform, convert, or map (hereinafter “map”) the geometric description to an equivalent parasitic value such as a resistance, capacitance or inductance.
  • This translation, transformation, conversion, or mapping (hereinafter “mapping") may be done with mathematical algorithms or models that are often referred to as parasitic extraction.
  • the models may be created through the use of semi-empirical methods that combine models or knowledge of the underlying physics with data provided by various solver(s), simulator(s), or a combination thereof. In some cases, the mapping for capacitance may also be done with a solver.
  • the second stage may use parasitic extraction for some nets and a field solver for other nets.
  • the second stage may use a combination of parasitic extraction for, for example, resistance(s) and a field solver for, for example, capacitance(s) on the same net.
  • the characterization of electrical parasitics may be performed with extraction tools that map geometric dimensions and patterns to corresponding parasitics such as R, L, and C.
  • the characterization of electrical parasitics includes the use of field solvers (such as but not limited to one or more EM field solvers) that map geometric dimensions and patterns to
  • the method or the system may further comprise the process or hardware module for characterizing one or more electrical parasitics that are associated with the physical data of the component at 154.
  • the physical data for a wire segment may comprise the material (e.g., Copper, Aluminum, or Tungsten), one or more physical attributes, such as the thermal conductivity, surface boundary activation energy, etc. and / or one or more electrical attributes, such as the electrical conductance, Blech distance, or electrical resistivity.
  • the material e.g., Copper, Aluminum, or Tungsten
  • one or more physical attributes such as the thermal conductivity, surface boundary activation energy, etc.
  • electrical attributes such as the electrical conductance, Blech distance, or electrical resistivity.
  • Fig. 2A further provides more details about the process or module of characterizing one or more electrical characteristics associated with one or more electrical parasitics in some embodiments.
  • the process or module may comprise identifying or determining current such as the peak current, the maximum sustained current, the average current, or the RMS current by performing simulation(s) for each terminal of a component, device, or net at 222.
  • the current waveforms, duty cycle(s), or frequency (frequencies) may also be considered in some embodiments.
  • the RMS currents may be used with analog designs or reliability critical applications where self-healing effect need not be considered.
  • the average currents may be used in, for example, some digital signal nets where self-healing effects need to be considered.
  • the process or module 206 may further comprise using a linear solver 224 for voltages or currents of a net, device, or component in some embodiments.
  • the process or module 206 may further comprise the use of the solved voltages and subsequent algebraic calculations using Ohm's law to determine the current(s) in each wire segment as well as the geometry of the wire segment to acquire or compute current(s) or voltage(s), or with additional computation, current density (or densities) (226) of a net, device, or component in some embodiments.
  • FIG. 2B which illustrates a more detailed diagram for the method or system for implementing electronic circuit design with electro- migration awareness and some detailed information about the process or module for characterizing one or more electrical characteristics that are associated with electrical parasitics, both of which are similar to the method, system, process, and module as illustrated in Fig. 2A and described in some of the preceding paragraphs.
  • Fig. 2B is provided to point out that the device related simulation from the schematic may often be done before any physical data is created. In this case, the simulation data is assembled, may be post-processed to compute peak, RMS or average values from the waveforms and may be stored for use during physical design.
  • linear solver based flow One requirement for the linear solver based flow is that the terminal currents be available for retrieval and use prior to invoking the linear solver to generate the currents and voltages in the interconnect. This figure is provided to illustrate that alternative flows may be used to bring simulation data into solver based flow.
  • the method or system for implementing electronic circuit designs with electro-migration awareness comprises the process or module for completing the schematic design of an electronic circuit design at 252.
  • the method or system for implementing electronic circuit designs with electro-migration awareness comprises the process or module for running simulation(s), assembling or computing electrical data such as current data or voltage data, and storing the computed electrical data at 254 in some embodiments.
  • the method or system for implementing electronic circuit designs with electro- migration awareness may proceed from 254 to 260 to invoke the process or the hardware module for characterizing one or more electrical characteristics that are associated with one or more electrical parasitics and the physical data of a component in the electronic circuit design in one or more embodiments.
  • the method or system for implementing electronic circuit designs with electro-migration awareness comprises the process or module for characterizing one or more electrical characteristics that are associated with the one or more electrical parasitics at 266.
  • the process or hardware module for characterizing the one or more electrical characteristics may comprise the
  • the electrical data comprise electrical current(s) such as peak current(s) or average current(s) for one or more terminals.
  • the process or hardware module for characterizing the one or more electrical characteristics may further comprise the corresponding process or hardware module for invoking or utilizing a solver, such as a linear matrix solver or a non-linear solver, at 270 to solve for or acquire one or more electrical data such as various current(s), voltage(s), or with additional computation, current density (or densities), at one or more components at 272.
  • a solver such as a linear matrix solver or a non-linear solver
  • Fig. 2C illustrates more detailed block diagrams for the method or system for implementing electronic circuit design with electro-migration awareness and some detailed information about the process or module for characterizing one or more electrical characteristics that are associated with electrical parasitics in some embodiments for characterizing the RMS currents flowing through, for example, a net to determine whether certain EM related constraints are satisfied.
  • the aforementioned approach comprises the processes or modules of identifying a complete schematic design of an electronic circuit at 252 and simulating, assembling or computing, and storing the information or data of various current(s) or voltage(s) in a computer readable storage medium.
  • the information or data of various current(s) or voltage(s) may be stored in a volatile memory, such as some random access memory, for a substantially real-time determination and characterization of whether at least a part of the electronic circuit complies with certain EM related constraints.
  • the information or data of various current(s) or voltage(s) may be stored in a non-volatile memory, such as a computer hard drive.
  • the method or system may also comprise the process or module, which is substantially similar to the process or module 204 or 258 as described in some preceding paragraphs with reference to Figs. 2A-B, for characterizing one or more electrical parasitic(s) that are associated with the physical data of the component.
  • the method or the system may comprise the process or module, which are substantially similar to the process or module 206 or 260 as described in some preceding paragraphs with reference to Figs. 2A-B, for characterizing one or more electrical characteristic(s) that are associated with the one or more electrical parasitics and the physical data of the component.
  • Fig. 2C further illustrates more details about the process or module
  • the method or the system may comprise the process or module for retrieving or identifying information or data of current(s) for, for example but not limited to, one or more current waveforms for each of the plurality of device terminals at 204C in some embodiments. The method or the system may then proceed to invoke the process or the module, which are substantially similar to the process or module 210 or 264 as described in some preceding paragraphs with reference to Figs.
  • a solver such as a linear matrix solver or a non-linear solver to solve for various current(s), voltage(s), current density (or densities), or other electrical behavior or characteristics as previously described for the process or module 226 or 272 in some embodiments.
  • Fig. 2D illustrates a flow diagram for more details about the process or module 206 or 260 for characterizing one or more electrical characteristics that are associated with the one or more electrical parasitics in some embodiments.
  • the process or module for characterizing one or more electrical characteristics may comprise the process or module 280 for retrieving or identifying information or data of various current(s) in at least a portion of the layout in one or more embodiments.
  • the layout constitutes a partial or incomplete (hereinafter partial) layout that does not and will not pass a Layout Versus Schematic (LVS) check or verification due to the lack of physical design for one or more components in the layout of the electronic circuit design.
  • LVS Layout Versus Schematic
  • the single terminal current may be distributed across multiple terminals as part of the synchronization that occurs between the layout and the schematic used as part of the simulation.
  • the process or module may further comprise the process or module, which are substantially similar to the process or module 224 or 270 as described in some preceding paragraphs with reference to Figs. 2A-B, to invoke a solver, such as a linear matrix solver or a non-linear solver, to solve for one or more electrical characteristics of the at least a portion of the layout (282) in some embodiments.
  • a solver such as a linear matrix solver or a non-linear solver
  • the one or more electrical characteristics comprise some current(s), voltage(s), or current density (or densities) at, for example, a terminal of a component, or through a segment of an interconnect.
  • Fig. 2E illustrates a flow diagram for more details about the solver
  • the process or module comprises using a plurality of resistance parasitics to construct an electrical conductance matrix (G) in some embodiments.
  • the electrical conductance matrix comprises elements each of which constitutes the reciprocal of a resistance of, for example, a segment of an interconnect.
  • the electrical conductance matrix (G) may be arranged in any manner that is suitable for solving for the electrical behavior or various electrical
  • the electrical conductance matrix (G) may be arranged in a manner such that the portion of the electronic circuit may be solved under the Kirchhoff's junction rule (or the Kirchhoff's current law or KCL).
  • the process or module comprises decomposing the electrical conductance matrix into an upper triangular matrix and a lower triangular matrix in some embodiments. In some embodiments where the electrical
  • the process or module may invoke, for example, some direct methods such as the Cholesky- based techniques or the LU decomposition techniques to decompose the electrical conductance matrix into the lower triangular matrix and the upper triangular matrix.
  • the process or the module may invoke other numerical techniques such as the conjugate gradient method or the biconjugate gradient method to achieve substantially the same purpose.
  • the process or module may comprise using forward and backward substitution to solve for one or more electrical characteristics in some embodiments.
  • the one or more electrical characteristics comprise various voltages at various nodes in the at least a portion of the electronic circuit design. In these embodiments where the one or more electrical
  • the process or module may further comprise using the various voltages to solve for various currents flowing through the component.
  • the determination of various currents may be sufficient to determine whether or not the portion of the electronic circuit design satisfies certain design rules.
  • Fig. 2F illustrates more details for the process or module for solving for currents, voltages, or current densities at 226 or 272.
  • the process or module for solving for various currents, voltages, or current densities at 226 or 272 may comprise using net shapes and currents determined at 290 to determine current densities for one or more EM related limits or constraints that are expressed in terms of current densities at 292.
  • the method or the system may determine the current densities through various parts of the portion of electronic circuit design and then determines whether the portion of the electronic circuit design satisfies the limits on current densities by comparing the determined current densities with the limits on current densities imposed by the design rules.
  • the process or module for solving for various currents, voltages, or current densities at 226 or 272 may comprise using currents for EM limits expressed in terms of maximum current that is computed for each net shape at 294. For example, certain foundries impose EM related constraints by imposing limits on current densities through various parts of the portion of the electronic circuit design.
  • some processes or modules are integrated with or integrally linked to some physical design implementation platform, such as a layout tool or editor, the physical shapes and thus the geometric information of these physical shapes in the portion of the electronic circuit design become available.
  • Fig. 2G illustrates a flow diagram for more detailed process or module for implementing electronic circuit design with electro-migration awareness in some embodiments. More specifically, Fig. 2G shows the example where peak currents constitute the electrical characteristics of interest for electro-migration aware electronic circuit design implementation and illustrates the process or module that constructs an electrical conductance matrix (G), decomposes the electrical conductance matrix once for electrical parasitics, and then uses the same
  • the term max refers to the maximum positive and maximum negative current values at each of N terminals, thus producing 2N current vectors.
  • the process or module may comprise identifying a set of 2N current vectors (I MAXI , IMAXN2, . . . , IMAXN , IMAXN+1 . . . IMAX2N) for a total of N or 2N terminals from one or more simulations at 202G in some embodiments.
  • the currents are bi-directional, both the positive maximum current and the maximum negative current are examined for each of the N terminals, and thus there are 2N column vectors for the 2N currents at these N terminals.
  • the process or module examines the maximum current at each terminal, and thus there are 2N column current vectors for 2N terminals in these embodiments.
  • the process or module further comprises selecting one of these 2N current vectors that are identified at 202G in some embodiments.
  • the process or module may further comprise characterizing one or more electrical parasitics that are associated with the physical data of the component of a portion of an electronic circuit design at 204G.
  • the process or module may further comprise using the one or more electrical parasitics, such as the resistance parasitics, to construct an electrical conductance matrix (G) in a manner that is substantially similar to that of 284 as described in some of the preceding paragraphs.
  • the process or module may then comprise decomposing the electrical conductance matrix (G) into an upper triangular matrix and a lower triangular matrix in a manner that is substantially similar to that of 286 as described in some of the preceding paragraphs in these embodiments.
  • the process or module may then uses, for example, forward substitution and backward
  • the process or module may then use the voltages to solve for currents that flow through the component for the current vector that is selected or identified at 206G in some embodiments.
  • the process or module may comprise identifying or determining one or more proper EM related constraints that are associated with the electrical characteristics in a manner that is substantially similar to that of 208 or 262 as described in some of the preceding paragraphs.
  • the process or module may further comprise ensuring the correctness of the physical data or other data related to the one or more EM related constraints in a manner that is substantially similar to that of 210 or 264 as described in some of the preceding paragraphs in some embodiments.
  • the process or module may then loop back to 206G to select the next current vector of the 2N vectors and repeats the above steps. In this example, the current vector for each terminal is examined to determine whether the corresponding EM related
  • Fig. 2H illustrates a flow diagram for more detailed process or module for implementing electronic circuit design with electro-migration awareness in some embodiments. More specifically, Fig. 2H shows the example where the RMS currents constitute the electrical characteristics of interest for electro-migration aware electronic circuit design implementation. In the cases where the RMS currents are of interest, the time trajectory of the current waveform or at least an approximate form of the time trajectory needs to be analyzed to determine whether certain EM related constraints are satisfied. In some embodiments where the process or modules as illustrated in Fig. 2H applies, the method or system
  • the method or system may further comprise characterizing one or more electrical characteristics that are associated with the physical data of a component of a portion of an electronic circuit design at 204H and proceeds to 284 to use the one or more electrical parasitics, such as resistance parasitics, to construct an electrical conductance matrix (G) in a manner that is substantially similar to that of 284 as described in some of the preceding paragraphs.
  • the method or system may further comprise decomposing the electrical conductance matrix (G) into an upper triangular matrix and a lower triangular matrix in a manner that is substantially similar to that of 286 as described in some of the preceding paragraphs.
  • the method or the system may then comprise using forward and backward substitution to solve for various voltages and solving for currents through the component by using at least the voltages at 290 in a manner that is substantially similar to that of 288 and 290 as described in some of the preceding paragraphs.
  • the method or system may then loop back to 206H to identify or select another current vector of the T column current vectors. Once all of the T column current vectors have been processed by using the processes or modules 206H, 288, and 290, the method or system may then proceed to 208H to compute the RMS values for, e.g., each net segment in some
  • the process or module may comprise identifying or determining one or more proper EM related constraints that are associated with the electrical characteristics in a manner that is substantially similar to that of 208 or 262 as described in some of the preceding paragraphs.
  • the process or module may further comprise ensuring the correctness of the physical data or other data related to the one or more EM related constraints in a manner that is substantially similar to that of 210 or 264 as described in some of the preceding paragraphs in some embodiments.
  • the method or system may loop back to 202H to further identify or select the next set of current vectors in some
  • the average values may be computed as part of the RMS computation from the current waveforms.
  • the two methods are similar in terms of decomposition of the conductance matrix and the solving for voltages and currents through each resistance element. As the RMS values are computed for each waveform, the average currents are computed as well. The RMS values are checked against RMS limits, and the average values checked against the average limits.
  • Fig. 2J illustrates a flow diagram for more detailed process or module for implementing electronic circuit design with electro-migration awareness in some embodiments. More specifically, Fig. 2J shows the example where the method or the system decomposes the electrical conductance matrix (G) once for the resistance parasitic (R) and uses the same decomposition for each of C column current vectors for corners that do not require a different resistance parasitic in some embodiments.
  • the method or the system may comprise identifying or determining a set of C column current vectors (lavg_cnri , lavg_cnri . . . lavg_cnrc ) that represent an average current vector for each of C corner values 202J.
  • the method or the system may further comprise identifying or selecting a column current vector from the set of C column current vectors at 206 J.
  • the method or the system may further comprise characterizing one or more electrical characteristics that are associated with the physical data of a component in at least a portion of the physical design of an electronic circuit design at 204J in a
  • the method or the system may also comprise using the one or more electrical parasitics (the resistance parasitics in this example as illustrated in Fig. 2J) to for a matrix.
  • the method or the system comprises using the resistance parasitics to construct an electrical conductance matrix (G) in a substantially similar manner as that of 284 described in some preceding paragraphs with reference to Figs. 2A-H.
  • the method or the system may further the process or module, which are substantially similar to the process or module 286 as described in some preceding paragraphs with reference to Figs. 2A-H, for decomposing the electrical conductance matrix into an upper triangular matrix and a lower triangular matrix.
  • the method or the system may comprise the process or module, which are substantially similar to the process or module 288 as described in some preceding paragraphs with reference to Figs. 2A-H, using forward and backward substitution to solve for some electrical characteristics in some embodiments.
  • the electrical characteristics being solved for comprise various voltages.
  • the method or the system may further comprise the process or module, which are substantially similar to the process or module 290 as described in some preceding paragraphs with reference to Figs. 2A-H, for using the various voltages that are determined at 288 to solve for current(s) throughout the component of interest at 290.
  • the method or the system may further determine whether there exist more column current vectors in the set of C column current vectors in some embodiments. The method or the system may then loop back to 206J to identify or select another column current vector from the set of C column current vectors in some embodiments where it is determined that there still exist some column current vectors in the set.
  • the method or the system may further comprise the process or module for determining the RMS value(s) for each segment of the net at 208J.
  • the method or the system may further comprise the process or module, which are substantially similar to the process or module 208 or 262 as described in some preceding paragraphs with reference to Figs. 2A-H, for identifying or determining one or more EM related constraints that are associated with the one or more electrical
  • the process or module may further comprise ensuring the correctness of the physical data or other data related to the one or more EM related constraints in a manner that is substantially similar to that of 210 or 264 as described in some of the preceding paragraphs in some embodiments.
  • the method or system may further return to select the next current vector in some embodiments.
  • the method or system performs various processes or invokes various modules as described herein with reference to various figures for implementing electronic circuit design while maintaining electro-migration awareness on a net by net basis.
  • the method or system performs various actions while operating on a partial layout that does not and will not pass the LVS check or verification.
  • various processes or modules need only a single net to perform their intended functions and to achieve their intended purposes.
  • various processes or modules described herein may be invoked to implement the electronic circuit design even when the physical design (e.g., the layout) contains the very first net in some embodiments.
  • the process or module 106 may further comprises performing simulation(s) at the schematic level in some embodiments at 312 and storing the original or compressed simulation result(s) or data in a non-transitory computer readable storage medium at 314.
  • a schematic circuit may be created and simulated to determine the electrical characteristics (such as the currents or voltages) of the circuit. In some embodiments as described herein, this may be done any time prior to solving for the electrical characteristics of the physical design.
  • simulation may be done upon completion of the schematic, and in this flow that simulation data or results may be stored in a database for retrieval later.
  • the simulation is operated at particular corners and analysis points, such as temperature, and the same settings are used during parasitic extraction.
  • the process or module 106 may further comprise
  • the process or module may then use a solver, for example a linear matrix solver, to solve for the electrical characteristics of the physical design of the electronic design at 318 in some embodiments.
  • the electrical characteristics comprise current(s), voltage(s), or current density (densities) that is associated with the physical data.
  • Fig. 3B illustrates a similar flow diagram for the process or module
  • the process or module 106 may further optionally comprise mapping schematic data to physical data or layout at 322.
  • the process or module 106 may map the currents or voltages identified or determined at the schematic level simulation to the physical data or layout to impart such schematic level data or results into the linear solver 318 in order for the linear solver 318 to determine the currents, voltages, or current densities at the physical level at 320.
  • the process or module 106 may comprise the process or module 106 for characterizing one or more electrical characteristics associated with one or more electrical parasitics comprises identifying or determining temperature or thermal data at 402 and imparting the temperature or thermal data into the process or module of
  • thermal maps where the estimated operating temperature varies across a device may be applied locally to estimate the correct parasitic elements. For example, certain resistances or capacitances may be expressed in terms of temperatures to characterize their temperature dependence.
  • various temperature or thermal data may also be imparted into the process or module of identifying or determining one or more EM related constraints that are associated with one or more electrical characteristics such as those in the processes or modules 208 or 262.
  • the process or the module may use one or more maximum temperature for each, for example but not limited to, terminal to identify or determine the one or more EM related
  • the process or the module may use one or more average temperatures to identify or determine the one or more EM related
  • the process or the module may use one or more appropriate temperatures, which is (are) determined based at least in part upon, for example, the predicted or guaranteed life of the electronic device, to identify or determine the one or more EM related constraints.
  • the temperature or thermal data may further be imparted into the process or module for specifying simulation parameters or analysis points or corners at 406 in some embodiments.
  • the simulation parameters or analysis points or corners may then be further imparted to the process or module 410 which performs one or more simulations at the schematic level.
  • the process or module 106 may further comprise mapping physical data or layout information to schematic level data at 404 in some embodiments.
  • the process or module 106 may further optionally comprise reducing the parasitics to an approximate form to speed up physical level simulation(s) that is to be performed at 410 in some embodiments.
  • the method or system may further comprise determining or assembling the current(s), voltage(s), or current density (densities) that is (are) associated with the physical data in some embodiments.
  • the physical data, the electrical parasitics, or the electrical characteristics are passed between the schematic domain and the physical domain such that both the schematic domain tools (such as a schematic level simulator) and the physical domain tools (such as the placement tool, the router, or the physical level simulators, etc.) are aware of such data while the physical design/layout is being implemented.
  • the schematic domain tools such as a schematic level simulator
  • the physical domain tools such as the placement tool, the router, or the physical level simulators, etc.
  • the process or module 106 may further comprise the process or module for manually entering voltage or current values or vectors (such as the RMS currents, the peak currents, the average currents, or the current waveforms, etc.) into the physical design at 502 in some embodiments.
  • voltage or current values or vectors such as the RMS currents, the peak currents, the average currents, or the current waveforms, etc.
  • the user/designer may do 'what-if analysis where currents and voltages may be manually entered for one or more nets where they don't exist or modified where they do exist.
  • the designer can intentionally modify these values to examine electrical parameter sets not computed or provided by simulation.
  • the person performing layout may not have access to simulation data but still wants to examine the impact of manually entered electrical parameters.
  • the manually entered voltages or currents are passed along into a linear solver to characterize the electrical characteristics in some
  • the linear solver may also consider one or more electrical parasitics that are characterized at 104 in characterizing the electrical characteristics that are associated with the electrical parasitics in some embodiments.
  • the process or module 106 may further comprise the process or module for assembling or determining the current(s), voltage(s), or current density (densities) that are associated with the physical data in some embodiments.
  • the method or system for implementing electronic circuit design with electro-migration awareness comprises identifying or determining one or more EM related constraints that are associated with the characterized electrical characteristics at 602.
  • the method or the system identifies or retrieves one or more EM related constraints.
  • the method or the system for implementing electronic circuit designs may further comprise checking the current or current density of a physical object against the one or more EM related constraints at 606.
  • the system is aware of the physical data, such as the width, length, or cross-sectional area of a circuit component at the physical level such as wire, via or via cluster, and thus the one or more EM related constraints may be provided in either current density format or current format.
  • Some embodiments may use physical data geometry to convert current density limits to maximum current(s) for a given object geometry so that the user can work solely with currents a metric that may be relate better or more intuitively to the expected circuit behavior.
  • Fig. 6 further illustrates more details for the process or module 602 for identifying or determining one or more EM related constraints that are associated with the characterized electrical characteristics associated with the characterized electrical parasitics and physical data.
  • the method or the system for implementing electronic circuit designs with electro-migration awareness proceeds to 608 to invoke a process or module for assembling or providing the relevant geometric parameters that are associated with the net, device, or component associated with the physical data of interest in a single embodiment or in some embodiments.
  • the relevant geometric parameters comprise a distance or length for the net, device, or component, which length represents the lower limit for the length of an interconnect below which electro- migration is not a concern.
  • the length or distance may comprise the Blech length.
  • the relevant geometric parameters may comprise the arrangement of a via array because the arrangement affects the distribution of current through each via in the via array.
  • the relevant geometric parameters comprise the corner bend configuration of an interconnect.
  • the electro-migration in an interconnect with a rounded corner bend configuration is less severe than that in a tapered bend configuration, which is in turn less severe than a corner bend of right angles. Therefore, some adjustments may need to be made in light of the corner bend configurations of a particular
  • an EM limit or constraint may be identified as a simple numerical value such as a maximum current density or maximum density.
  • an EM limit or constraint may be identified as a function or functional of geometry of the net, device, or component associated with the physical data 612. For example, the lengths of certain wires or interconnects may be under the Blech length, and thus electro-migration is not a concern for such wires or interconnects.
  • an EM related constraint may be provided as a function of via groups or arrays.
  • an EM related constraint may be provided as a function of the net attribute such as signal, power/ground.
  • an EM related constraint may be provided as a function of the duty or pulse characteristics of a particular signal.
  • the process or module 602 further comprises determining whether the one or more characterized electrical
  • the process or module 602 may check a wire segment or a via to determine whether the current (such as the RMS current, the peak current, the average current, or the current waveform) or the current density meets the corresponding maximum current or current density constraint.
  • the method or the system as illustrated in Fig. 6 depicts an approach that for each physical data object, e.g. wire segment, via, via cluster, currents or current densities in the physical data object may be compared with the maximum current or maximum current density limits that are prescribed in one or more EM related constraints in some embodiments.
  • the EM limits or constraints may be based on geometric characteristics of the physical data, for example some wire segments may be under the Blech length and thus EM is not a factor.
  • the limits or constraints are compared to the electrical characteristics.
  • the method or the system further provides the capability to notify the user through a graphical user interface when the limits or constraints are exceeded in some embodiments.
  • the physical geometries, e.g. wire width, of the data object may be computed such the limit is not exceeded in some embodiments.
  • these changes may be displayed as a hint to the user for manual fixing or the changes may be made automatically in some
  • each route is created, checked for EM correctness and if necessary corrected before moving to the next route in these embodiments.
  • the EM checking flow as described herein in various embodiments may be further combined with current, voltage, resistance, or capacitance constraints that are created or identified prior to physical design.
  • Fig. 7 which illustrates a more detailed flow diagram for the method or system for implementing electronic circuit designs with electro- migration awareness
  • the method or the system for implementing electronic circuit designs with electro-migration awareness comprises the process or module of identifying, determining, updating the physical data of a net, a device, or a
  • the method or the system may further comprise the process or module of characterizing one or more electrical parasitics associated with the physical data at 704 and the process or module of characterizing one or more electrical characteristics associated with the one or more electrical parasitics at 706 in a single embodiment or in some embodiments.
  • the method or the system may further comprise the process or module of identifying or determining one or more EM related constraint associated with the one or more electrical characteristics at 708 in some embodiments.
  • the method or the system may further optionally comprise the process or module of ensuring correctness of the physical data or other data related to the one or more EM related constraints in some embodiments at 710.
  • the details of the processes or modules of 702, 704, 706, 708, and 710 have been described in previous paragraphs with reference to Figs. 1 -6 and will not be repeated here.
  • the method or the system may further optionally comprise the process or module of computing or determining one or more adjustments or providing one or more hints to correct the physical data at 712.
  • the method or the system may determine or compute one or more adjustments to the width which, when made, will cause the wire segment to meet the current density EM constraint or may provide a hint, such as widen the width of the wire segment to .16 ⁇ , or simply widen the width of the wire segment without specific numerical values, or reconfigure the bend at (x, y) location, to the user such that the user may know where the EM violation is and / or how to fix the EM violation.
  • Fig. 8 which illustrates a more detailed flow diagram for the method or system for implementing electronic circuit designs with electro- migration awareness
  • the method or the system for implementing electronic circuit designs with electro-migration awareness comprises the process or module of identifying, determining, updating the physical data of a net, a device, or a
  • the method or the system may further comprise the process or module of characterizing one or more electrical parasitics associated with the physical data at 804 and the process or module of characterizing one or more electrical characteristics associated with the one or more electrical parasitics at 806 in a single embodiment or in some embodiments.
  • the method or the system may further comprise the process or module of identifying or determining one or more EM related constraint associated with the one or more electrical characteristics at 808 in some embodiments.
  • the method or the system may further optionally comprise the process or module of ensuring correctness of the physical data or other data related to the one or more EM related constraints in some embodiments at 810.
  • the method or the system may further optionally comprise the process or module of computing or determining one or more adjustments or providing one or more hints to correct the physical data at 812.
  • the details of the processes or modules of 802, 804, 806, 808, 810, and 812 have been described in previous paragraphs with reference to Figs. 1 -6 and will not be repeated here.
  • the method or the system may further optionally comprise the process or module of determining or checking to ensure whether or not one or more adjustments or hints violate other one or more design rules or constraints at 814.
  • an EM violation may result in the widening of a wire to reduce the current density below a limit but may also increase coupling capacitance to an adjacent neighbor beyond an established constraint.
  • the method or the system may proceed to apply the one or more adjustments to fix the physical design in some embodiments, or may display one or more hints to the user in some other embodiments.
  • the method or the system may apply the one or more adjustments to fix the physical data at 816.
  • the method or the system may still apply the one or more adjustments to fix the physical data and present the violations of the one or more other design rules or constraints to the user.
  • the method or the system may further fine tune the one or more adjustments determined or computed at 812 or may determine or compute other adjustments to address the violations caused by the one or more adjustments.
  • the method or the system may further optionally present one or more hints involving these other adjustments to the user or may apply these other adjustments to fix the violations caused by the one or more adjustments determined or computed at 812.
  • Fig. 9 illustrates a more detailed flow diagram for the method or system for implementing electronic circuit designs with electro- migration awareness
  • the processes or modules 902, 904, 906, 908, 910, 912, and 914 correspond to the substantially similar processes or modules 802, 804, 806, 808, 810, 812, and 814 and thus will not be repeated here to avoid duplication of records.
  • the method or the system for implementing electronic circuit designs with electro- migration awareness may further comprise the process or module of applying the one or more adjustments that are determined or computed at 912 to the net, device, or component or the associated physical data at 916 in some embodiments.
  • the method or the system may further loop back to 902 to further determine whether there exist a need to further identify or determine another net, device, or component, or whether the existing identified or determined net, device, or component needs to be updated after the application of the one or more adjustments at 912.
  • the method or the system then proceeds through the process flow as described in various embodiments with reference to various figures until the physical design is complete.
  • the method or the system implements the physical design of an electronic circuit while being aware of electro-migration related constraints or rules in some embodiments.
  • the method or the system is aware of the electro-migration related design rules or constraints while the method or the system is implementing the nets, devices, components, or even the first net, first device, or first component into the physical design of the electronic circuit design.
  • FIG. 10 illustrates a block diagram of an illustrative computing system 1400 suitable for implementing some embodiments of the method or system for implementing electronic circuit designs with electro- migration awareness as described in the preceding paragraphs with reference to various figures.
  • Computer system 1400 includes a bus 1406 or other
  • communication mechanism for communicating information which interconnects subsystems and devices, such as processor 1407, system memory 1408 (e.g., RAM), static storage device 1409 (e.g., ROM), disk drive 1410 (e.g., magnetic or optical), communication interface 1414 (e.g., modem or Ethernet card), display 141 1 (e.g., CRT or LCD), input device 1412 (e.g., keyboard), and cursor control (not shown).
  • processor 1407 system memory 1408 (e.g., RAM), static storage device 1409 (e.g., ROM), disk drive 1410 (e.g., magnetic or optical), communication interface 1414 (e.g., modem or Ethernet card), display 141 1 (e.g., CRT or LCD), input device 1412 (e.g., keyboard), and cursor control (not shown).
  • system memory 1408 e.g., RAM
  • static storage device 1409 e.g., ROM
  • disk drive 1410 e.g., magnetic or optical
  • computer system 1400 performs specific operations by one or more processor or processor cores 1407 executing one or more sequences of one or more instructions contained in system memory 1408. Such instructions may be read into system memory 1408 from another computer readable/usable storage medium, such as static storage device 1409 or disk drive 1410. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to
  • embodiments of the invention are not limited to any specific combination of hardware circuitry and/or software.
  • the term "logic” shall mean any combination of software or hardware that is used to implement all or part of the invention.
  • Various actions or processes as described in the preceding paragraphs may be performed by using one or more processors, one or more processor cores, or combination thereof 1407, where the one or more processors, one or more processor cores, or combination thereof executes one or more threads.
  • the act of specifying various net or terminal sets or the act or module of performing verification or simulation, etc. may be performed by one or more processors, one or more processor cores, or combination thereof.
  • the parasitic extraction, current solving, current density computation and current or current density verification is done in memory as layout shapes or nets are created or modified.

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Abstract

Cette invention se rapporte à des procédés, à des systèmes et à des articles de fabrication destinés à mettre en application des conceptions de circuit électronique avec une prise de conscience d'électromigration. Certains modes de réalisation exécutent une ou des simulations au niveau schématique de façon à déterminer des caractéristiques électriques, identifient des parasites physiques d'un composant d'implantation, déterminent les caractéristiques électriques ou physiques associées à une analyse d'électromigration sur le composant et déterminent si le composant satisfait à une ou à des contraintes d'EM associées tout en mettant en application la conception physique du circuit électronique dans certains modes de réalisation. Certains modes de réalisation déterminent en outre un ou des réglages sur le composant ou des données associées où les contraintes d'EM associées ne sont pas satisfaites et/ou présentent le ou les réglages sous une forme de conseils. Diverses données et informations, telles que des courants sous diverses formes ou des tensions, sont transmises entre les divers outils au niveau schématique et les outils au niveau physique.
PCT/US2011/045104 2010-07-24 2011-07-22 Procédés, systèmes et articles de fabrication destinés à mettre en application des conceptions de circuit électronique avec une prise de conscience d'électromigration WO2012018571A1 (fr)

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