FR2888014B1 - Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test - Google Patents

Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test

Info

Publication number
FR2888014B1
FR2888014B1 FR0507050A FR0507050A FR2888014B1 FR 2888014 B1 FR2888014 B1 FR 2888014B1 FR 0507050 A FR0507050 A FR 0507050A FR 0507050 A FR0507050 A FR 0507050A FR 2888014 B1 FR2888014 B1 FR 2888014B1
Authority
FR
France
Prior art keywords
chains
location
determining
test
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0507050A
Other languages
English (en)
Other versions
FR2888014A1 (fr
Inventor
Poorter Alexandre De
Fabrice Picot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to FR0507050A priority Critical patent/FR2888014B1/fr
Priority to US11/207,082 priority patent/US7392448B2/en
Priority to PCT/US2006/025122 priority patent/WO2007005446A2/fr
Priority to TW095123277A priority patent/TW200714908A/zh
Publication of FR2888014A1 publication Critical patent/FR2888014A1/fr
Application granted granted Critical
Publication of FR2888014B1 publication Critical patent/FR2888014B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
FR0507050A 2005-07-01 2005-07-01 Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test Expired - Fee Related FR2888014B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0507050A FR2888014B1 (fr) 2005-07-01 2005-07-01 Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test
US11/207,082 US7392448B2 (en) 2005-07-01 2005-08-17 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains
PCT/US2006/025122 WO2007005446A2 (fr) 2005-07-01 2006-06-27 Procede et dispositif pour determiner les emplacements de defauts de collage dans des chaines de cellules au moyen de chaines de test
TW095123277A TW200714908A (en) 2005-07-01 2006-06-28 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0507050A FR2888014B1 (fr) 2005-07-01 2005-07-01 Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test

Publications (2)

Publication Number Publication Date
FR2888014A1 FR2888014A1 (fr) 2007-01-05
FR2888014B1 true FR2888014B1 (fr) 2007-09-21

Family

ID=36090886

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0507050A Expired - Fee Related FR2888014B1 (fr) 2005-07-01 2005-07-01 Procede et dispositif pour determiner l'emplacement de defauts de collage dans des chaines de cellules utilisant des chaines de test

Country Status (3)

Country Link
US (1) US7392448B2 (fr)
FR (1) FR2888014B1 (fr)
TW (1) TW200714908A (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008117372A (ja) * 2006-10-13 2008-05-22 Nec Electronics Corp 半導体集積回路およびその制御方法
US8316265B2 (en) * 2007-03-04 2012-11-20 Mentor Graphics Corporation Test pattern generation for diagnosing scan chain failures
US8261142B2 (en) 2007-03-04 2012-09-04 Mentor Graphics Corporation Generating test sets for diagnosing scan chain failures
US7755960B2 (en) * 2007-12-17 2010-07-13 Stmicroelectronics Sa Memory including a performance test circuit
TWI403745B (zh) * 2009-01-17 2013-08-01 Univ Nat Taiwan 非同步掃描鍊電路
US8566657B2 (en) * 2011-04-26 2013-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Circuit and method for diagnosing scan chain failures
US9274171B1 (en) 2014-11-12 2016-03-01 International Business Machines Corporation Customer-transparent logic redundancy for improved yield

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903466A (en) 1995-12-29 1999-05-11 Synopsys, Inc. Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design
US6157210A (en) 1997-10-16 2000-12-05 Altera Corporation Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits
US6158032A (en) * 1998-03-27 2000-12-05 International Business Machines Corporation Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof
US6526562B1 (en) 1999-05-10 2003-02-25 Analog Devices, Inc. Methods for developing an integrated circuit chip design
US6430718B1 (en) * 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US6587981B1 (en) 1999-11-29 2003-07-01 Agilent Technologies, Inc. Integrated circuit with scan test structure
US6490702B1 (en) 1999-12-28 2002-12-03 International Business Machines Corporation Scan structure for improving transition fault coverage and scan diagnostics
US6453436B1 (en) 1999-12-28 2002-09-17 International Business Machines Corporation Method and apparatus for improving transition fault testability of semiconductor chips
US6539536B1 (en) 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
US6694454B1 (en) 2000-06-30 2004-02-17 International Business Machines Corporation Stuck and transient fault diagnostic system
US6536007B1 (en) 2000-06-30 2003-03-18 Intel Corporation Models and technique for automated fault isolation of open defects in logic
US6546526B2 (en) 2001-01-19 2003-04-08 Springsoft, Inc. Active trace debugging for hardware description languages
US6957403B2 (en) 2001-03-30 2005-10-18 Syntest Technologies, Inc. Computer-aided design system to automate scan synthesis at register-transfer level
DE10116746A1 (de) * 2001-04-04 2002-10-17 Infineon Technologies Ag Datenverarbeitungsschaltung
US6701476B2 (en) * 2001-05-29 2004-03-02 Motorola, Inc. Test access mechanism for supporting a configurable built-in self-test circuit and method thereof
JP2003014819A (ja) * 2001-07-03 2003-01-15 Matsushita Electric Ind Co Ltd 半導体配線基板，半導体デバイス，半導体デバイスのテスト方法及びその実装方法
US7308631B2 (en) * 2002-09-13 2007-12-11 Arm Limited Wrapper serial scan chain functional segmentation
US7139950B2 (en) * 2004-01-28 2006-11-21 International Business Machines Corporation Segmented scan chains with dynamic reconfigurations
KR20050078704A (ko) * 2004-01-31 2005-08-08 삼성전자주식회사 스캔 베이스 ａｔｐｇ 테스트회로, 테스트방법 및 스캔체인 재배열방법
JP2006329876A (ja) * 2005-05-27 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法

Also Published As

Publication number Publication date
US7392448B2 (en) 2008-06-24
US20070022340A1 (en) 2007-01-25
TW200714908A (en) 2007-04-16
FR2888014A1 (fr) 2007-01-05

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Legal Events

Date Code Title Description
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Effective date: 20110331