FR2867606B1 - Procede et dispositif de traitement de la couche utile d'une structure multicouche - Google Patents

Procede et dispositif de traitement de la couche utile d'une structure multicouche

Info

Publication number
FR2867606B1
FR2867606B1 FR0402473A FR0402473A FR2867606B1 FR 2867606 B1 FR2867606 B1 FR 2867606B1 FR 0402473 A FR0402473 A FR 0402473A FR 0402473 A FR0402473 A FR 0402473A FR 2867606 B1 FR2867606 B1 FR 2867606B1
Authority
FR
France
Prior art keywords
processing
multilayer structure
useful layer
useful
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0402473A
Other languages
English (en)
Other versions
FR2867606A1 (fr
Inventor
Francois Brunier
Frederic Allibert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0402473A priority Critical patent/FR2867606B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to CN200580012304.9A priority patent/CN1947248B/zh
Priority to PCT/IB2005/000832 priority patent/WO2005088716A2/fr
Priority to EP05708800A priority patent/EP1723671A2/fr
Priority to KR1020067018525A priority patent/KR100828113B1/ko
Priority to JP2007502438A priority patent/JP4510876B2/ja
Publication of FR2867606A1 publication Critical patent/FR2867606A1/fr
Priority to US11/433,713 priority patent/US7790048B2/en
Application granted granted Critical
Publication of FR2867606B1 publication Critical patent/FR2867606B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
FR0402473A 2004-03-10 2004-03-10 Procede et dispositif de traitement de la couche utile d'une structure multicouche Expired - Fee Related FR2867606B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0402473A FR2867606B1 (fr) 2004-03-10 2004-03-10 Procede et dispositif de traitement de la couche utile d'une structure multicouche
PCT/IB2005/000832 WO2005088716A2 (fr) 2004-03-10 2005-03-10 Procede et dispositif de traitement de la couche de travail d'une structure multicouche
EP05708800A EP1723671A2 (fr) 2004-03-10 2005-03-10 Procede et dispositif de traitement de la couche de travail d'une structure multicouche
KR1020067018525A KR100828113B1 (ko) 2004-03-10 2005-03-10 다층구조의 가공층 처리 방법 및 장치
CN200580012304.9A CN1947248B (zh) 2004-03-10 2005-03-10 多层结构的工作层的处理方法及其器件
JP2007502438A JP4510876B2 (ja) 2004-03-10 2005-03-10 多層構造の作動層の処理方法および処理デバイス
US11/433,713 US7790048B2 (en) 2004-03-10 2006-05-12 Treatment of the working layer of a multilayer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0402473A FR2867606B1 (fr) 2004-03-10 2004-03-10 Procede et dispositif de traitement de la couche utile d'une structure multicouche

Publications (2)

Publication Number Publication Date
FR2867606A1 FR2867606A1 (fr) 2005-09-16
FR2867606B1 true FR2867606B1 (fr) 2006-06-02

Family

ID=34896418

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0402473A Expired - Fee Related FR2867606B1 (fr) 2004-03-10 2004-03-10 Procede et dispositif de traitement de la couche utile d'une structure multicouche

Country Status (7)

Country Link
US (1) US7790048B2 (fr)
EP (1) EP1723671A2 (fr)
JP (1) JP4510876B2 (fr)
KR (1) KR100828113B1 (fr)
CN (1) CN1947248B (fr)
FR (1) FR2867606B1 (fr)
WO (1) WO2005088716A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2867606B1 (fr) 2004-03-10 2006-06-02 Soitec Silicon On Insulator Procede et dispositif de traitement de la couche utile d'une structure multicouche
EP1998374A3 (fr) * 2005-09-29 2012-01-18 Semiconductor Energy Laboratory Co, Ltd. Dispositif de semi-conducteur disposant d'une couche de semi-conducteur d'oxyde et son procédé de fabrication

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1065903B (de) * 1955-09-09 1959-09-24 Sylvania Electric Products Incorporated, eine Gesellschaft nach den Gesetzen des Staates Delaware, New York, N. Y. (V. St. A.) Verfahren und Vorrichtung zur Herstellung von leitenden Mustern
JPS56123376A (en) 1980-02-28 1981-09-28 Fujitsu Ltd Etching method
JPS5948945A (ja) 1982-09-14 1984-03-21 Hitachi Cable Ltd 半導体用リ−ドフレ−ムの製造方法
US4668083A (en) 1985-11-18 1987-05-26 The Perkin-Elmer Corporation Contact lithographic fabrication of patterns on large optics
US5519336A (en) * 1992-03-03 1996-05-21 Honeywell Inc. Method for electrically characterizing the insulator in SOI devices
US5433821A (en) * 1994-02-25 1995-07-18 International Business Machines Corporation Direct patternization device and method
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
KR100333155B1 (ko) * 1994-09-16 2002-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막반도체장치및그제조방법
US5786231A (en) * 1995-12-05 1998-07-28 Sandia Corporation Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer
US6159829A (en) * 1996-09-16 2000-12-12 Warren; William L. Memory device using movement of protons
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
DE19828969A1 (de) * 1998-06-29 1999-12-30 Siemens Ag Verfahren zur Herstellung von Halbleiterbauelementen
AT408158B (de) 1998-12-28 2001-09-25 Kroener Friedrich Dr Maske zur strukturierten, elektrochemischen bearbeitung eines siliziumplättchens für die solarzellenherstellung
JP2003173951A (ja) * 2001-12-04 2003-06-20 Tokyo Electron Ltd 電子ビーム描画用マスクの製造方法および電子ビーム描画用マスクブランクス
FR2867606B1 (fr) 2004-03-10 2006-06-02 Soitec Silicon On Insulator Procede et dispositif de traitement de la couche utile d'une structure multicouche

Also Published As

Publication number Publication date
US7790048B2 (en) 2010-09-07
US20060201907A1 (en) 2006-09-14
KR100828113B1 (ko) 2008-05-08
WO2005088716A3 (fr) 2006-09-21
CN1947248B (zh) 2010-07-21
EP1723671A2 (fr) 2006-11-22
KR20060118604A (ko) 2006-11-23
WO2005088716A2 (fr) 2005-09-22
CN1947248A (zh) 2007-04-11
FR2867606A1 (fr) 2005-09-16
JP4510876B2 (ja) 2010-07-28
JP2007528597A (ja) 2007-10-11

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20131129