FR2855285B1 - ARBITRATOR, SYSTEM AND METHOD FOR GENERATING A PSEUDO-ACCORD SIGNAL IN A COMPUTER SYSTEM - Google Patents

ARBITRATOR, SYSTEM AND METHOD FOR GENERATING A PSEUDO-ACCORD SIGNAL IN A COMPUTER SYSTEM

Info

Publication number
FR2855285B1
FR2855285B1 FR0405490A FR0405490A FR2855285B1 FR 2855285 B1 FR2855285 B1 FR 2855285B1 FR 0405490 A FR0405490 A FR 0405490A FR 0405490 A FR0405490 A FR 0405490A FR 2855285 B1 FR2855285 B1 FR 2855285B1
Authority
FR
France
Prior art keywords
arbitrator
pseudo
generating
computer system
accord
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0405490A
Other languages
French (fr)
Other versions
FR2855285A1 (en
Inventor
Young Doug Kim
Kyoung Mook Lim
Nak Hee Seong
Seh Woong Jeong
Jae Hong Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020030033048A external-priority patent/KR100626362B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2855285A1 publication Critical patent/FR2855285A1/en
Application granted granted Critical
Publication of FR2855285B1 publication Critical patent/FR2855285B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
FR0405490A 2003-05-23 2004-05-19 ARBITRATOR, SYSTEM AND METHOD FOR GENERATING A PSEUDO-ACCORD SIGNAL IN A COMPUTER SYSTEM Expired - Fee Related FR2855285B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030033048A KR100626362B1 (en) 2003-05-23 2003-05-23 Arbiter and method for arbitrating high-performance bandwidth system bus and bus system having arbiter
US10/737,124 US8209453B2 (en) 2003-05-23 2003-12-17 Arbiter, a system and a method for generating a pseudo-grant signal

Publications (2)

Publication Number Publication Date
FR2855285A1 FR2855285A1 (en) 2004-11-26
FR2855285B1 true FR2855285B1 (en) 2006-07-07

Family

ID=33422295

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0405490A Expired - Fee Related FR2855285B1 (en) 2003-05-23 2004-05-19 ARBITRATOR, SYSTEM AND METHOD FOR GENERATING A PSEUDO-ACCORD SIGNAL IN A COMPUTER SYSTEM

Country Status (4)

Country Link
JP (1) JP4684577B2 (en)
CN (1) CN100419722C (en)
DE (1) DE102004024849B4 (en)
FR (1) FR2855285B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726101B1 (en) * 2005-04-29 2007-06-12 (주)씨앤에스 테크놀로지 System for Controlling Memory
KR101153712B1 (en) * 2005-09-27 2012-07-03 삼성전자주식회사 Apparatus and method for access controlling multi-port SDRAM
US9497710B2 (en) * 2013-11-25 2016-11-15 Qualcomm Incorporated Multipoint interface shortest pulse width priority resolution
CN114489541A (en) * 2022-01-14 2022-05-13 山东云海国创云计算装备产业创新中心有限公司 VGA video memory bandwidth regulation and control method based on FPGA and related components

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195469A (en) * 1984-10-16 1986-05-14 Fujitsu Ltd Competition control system of multiprocessor
JPS61210463A (en) * 1985-03-14 1986-09-18 Fujitsu Ltd Data transfer control system
US4947368A (en) * 1987-05-01 1990-08-07 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US6073199A (en) * 1997-10-06 2000-06-06 Cisco Technology, Inc. History-based bus arbitration with hidden re-arbitration during wait cycles
US6393506B1 (en) * 1999-06-15 2002-05-21 National Semiconductor Corporation Virtual channel bus and system architecture
US6718422B1 (en) * 1999-07-29 2004-04-06 International Business Machines Corporation Enhanced bus arbiter utilizing variable priority and fairness
CN100445973C (en) * 2002-04-17 2008-12-24 威盛电子股份有限公司 Method for arbitrating bus control right and its arbitrator

Also Published As

Publication number Publication date
JP2004348745A (en) 2004-12-09
FR2855285A1 (en) 2004-11-26
DE102004024849B4 (en) 2008-11-27
CN100419722C (en) 2008-09-17
JP4684577B2 (en) 2011-05-18
CN1573721A (en) 2005-02-02
DE102004024849A1 (en) 2004-12-23

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20100129