CN1573721A - Arbiter, a system and a method for generating a pseudo-grant signal - Google Patents
Arbiter, a system and a method for generating a pseudo-grant signal Download PDFInfo
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- CN1573721A CN1573721A CNA2004100459127A CN200410045912A CN1573721A CN 1573721 A CN1573721 A CN 1573721A CN A2004100459127 A CNA2004100459127 A CN A2004100459127A CN 200410045912 A CN200410045912 A CN 200410045912A CN 1573721 A CN1573721 A CN 1573721A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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- General Engineering & Computer Science (AREA)
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- Data Exchanges In Wide-Area Networks (AREA)
Abstract
An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.
Description
According to 35U.S.C § 119, this U.S. is non-please to require the right of priority of the korean patent application submitted on May 23rd, 2003 2003-33048 number in interim, and its content is quoted by integral body and is incorporated into this.
Technical field
The present invention relates to be used to generate moderator, the system and method for pseudo-grant signal (pseudo-grant signal).
Background technology
Become known for improving the arbitration body of the bus bandwidth between at least one main equipment (master) and at least one target slave unit (slave).The basic operation of such arbitration comprises request, arbitrates, authorizes with data and transmit.
When moderator is authorized bus entitlement to the main equipment of request access target slave unit, and slave unit be can't provide data to transmit the time, because main equipment must wait for that it is available transmitting for described data up to the target slave unit, the result is the waste that entitlement is authorized.When the main equipment access had the target slave unit of high latency, bandwidth also was lowered.
Fig. 1 example traditional sequential chart, its example stand-by period T.As shown in Figure 1, providing the first group address message ADDR1-4, is first group of data DATA D1-D4 subsequently.Then, providing the second group address message ADDR5-8, is second group of data DATA D5-D8 subsequently.As shown in Figure 1, stand-by period T is the delay between the availability of data DATA D4 and D5.This delay is undesirable.Fig. 2 shows the desirable sequential chart of having eliminated stand-by period T therein.
The memory field intersect (bank interleaving) be used as storer be divided into several memory fields, thereby allow traditional technology of each memory field of consecutive access.In the memory field intersects, be overlapping to each the operation in two memory fields, for example, access data pre-loaded data in another memory field simultaneously in a memory field are to improve bus bandwidth.
But the memory field intersection exists defective.Specifically, only after main equipment received based on the bus entitlement of arbitrating, this main equipment just drove effective address and control information.Therefore, because this information produces after arbitration, this information can not be used to arbitration.As a result, the improvement of bandwidth is restricted.In addition, owing to the request that can't send in advance, therefore still exist stand-by period to postpone such as above-mentioned T for the target slave unit.
Other legacy equipments comprise makes main equipment generate the period type signal in request.Whether the indication of period type signal will and will read or write this target by the specific target source (slave unit) of access.Based on period type signal and relevant target source information, moderator is determined the proprietorial priority of bus.In this mode, avoided the retry period of target slave unit and can improve bus bandwidth and overall system performance.But, need extra pin to come type signal and performance period because can not send request in advance to the target slave unit, still exist stand-by period to postpone such as T.
Fig. 3 illustrates traditional bus structure, comprises main equipment 1-3, moderator 4, sdram controller 5, sdram memory district 6.Each main equipment 1-3 asks bus access via the HBUSREQN signal from moderator 4.The moderator 4 that comprises one the arbitrated logic that is used for selecting main equipment 1-3 is arbitrated, and authorizes access to bus via the HGRANTN signal, described HGRANTN signal be provided among the main equipment 1-3 selected that.As shown in Figure 3, HADDRN, HWRITEN, HBURSTN, HSIZEN and HTRANN signal each all be the signal that drives the target slave unit.These signals provide to sdram controller 5 from main equipment 1-3 via one or more multiplexers (MUX) 7-8.MUX7-8 receives the HMASTER signal from moderator 4, and selected HDDR, HWRITER, HBURSTER, HSIZER and/or HTRANR are sent to sdram controller 5.MUX7 receives a HWDATAN signal from each of main equipment 1-3, and selected that in a plurality of HWDATAN signals is sent to sdram controller 5 as the BIWDATA signal.Sdram controller 5 sends BIREADYD signal each to the main equipment 1-3 after being ready to.Sdram controller 5 is switching signal and data to and fro also and between the SDRAM6.
Fig. 4 illustrates the sequential chart of conventional bus structure.As indicated among Fig. 4, between the transmission of the first data B0D0-B0D3 and the second data B1D0-B1D3, there is stand-by period T.This stand-by period, T reduced bus bandwidth efficient, and this stand-by period can't the request target slave unit be caused for data access this fact of preparing before receiving bus entitlement by arbitration by moderator.
Summary of the invention
In example embodiment, the present invention is directed to a moderator in the system, this moderator is used for generating pseudo-grant signal to all request main equipment unit; Receive transaction information in response to this pseudo-grant signal from all request main equipment unit with being used for.
In example embodiment, the present invention is directed to a kind of system, this system comprises: at least one is used to the main equipment unit of the request that generates, be used for from least one main equipment unit reception request, and being used for generating the moderator of pseudo-grant signal in response to request from least one main equipment unit, at least one provides the main equipment unit of target information to moderator in response to pseudo-grant signal; Is that data transmit the slave unit unit of preparing with at least one in response to the target information that is provided by described at least one main equipment unit.
In example embodiment, the present invention is directed to a kind of method of in system, arbitrating, this method comprises: generate pseudo-grant signal and respond described pseudo-grant signal receiving target information in response to request.
In example embodiment, the present invention is directed to a kind of method of in system, arbitrating, this method comprises: generate request; Receive described request and generate pseudo-grant signal in response to this request; Provide target information in response to described pseudo-grant signal; Be that data transmit and to prepare in response to described target information.
Description of drawings
According to detailed description given below and accompanying drawing, can more comprehensively understand the present invention, wherein provide accompanying drawing and be for the purpose of illustration only illustrative purposes, because of rather than be used to limit the invention.
Fig. 1 illustrates traditional sequential chart, and it shows stand-by period T.
Fig. 2 illustrates the sequential chart of hope, has wherein removed stand-by period T.
Fig. 3 illustrates traditional bus structure.
Fig. 4 illustrates the sequential chart of conventional bus structure;
Fig. 5 illustrates the bus arbitration structure according to illustrated embodiments of the invention.
Fig. 6 illustrates the sequential chart according to illustrated embodiments of the invention.
That Fig. 7 illustrates is more concrete, according to the bus structure of Fig. 5 of illustrated embodiments of the invention.
Fig. 8 illustrates the concrete structure of the another kind of example of versabus moderator scheme shown in Figure 5.
Fig. 9 illustrates according to example sequential chart of the present invention.
Figure 10 illustrates according to main interface illustrated embodiments of the invention, shown in Fig. 7 or 8.
Figure 11 illustrates the process flow diagram according to the phase one of the method for illustrated embodiments of the invention.
Figure 12 illustrates the process flow diagram according to the subordinate phase of the method for illustrated embodiments of the invention.
Embodiment
Fig. 5 illustrates the bus arbitration structure according to illustrated embodiments of the invention.As shown in Figure 5, the bus arbitration structure comprises: N main equipment unit 110,120,130, and wherein N is more than or equal to 1; Moderator 140; And M slave unit unit 150,160,170, wherein M is greater than 1 and needn't equal N.In operation, each main equipment unit 110,120,130 sends a request HBUSREQN to moderator 140.The HBUSREQ signal is a request signal that the target slave unit of for example slave unit 150,160 or 170 is carried out access.Moderator 140 each in N request main equipment unit 110,120,130 provides a pseudo-grant signal HGRANT.The HGRANT signal is to authorize bus proprietorial signal to main equipment.Then, each in N main equipment unit 110,120,130 provides target information to moderator 140, is used to make moderator 140 to arbitrate.In the example embodiment of graphic extension, target information is signal HADDRN in Fig. 5.Moderator 140 is arbitrated, and will produce the data transmission by providing ready signal HREADYN to indicate to each main equipment 110,120.
When two or more main equipments 110,120,130 are asked ACCESS bus, then state the HBUSREQN signal.In an exemplary embodiment of the present invention, in such circumstances, moderator 140 is authorized " vacation " or " puppet " entitlement by returned the HGRANTN signal before arbitration to all request main equipments 110,120,130.Main equipment 110,120,130 receives the bus entitlement, drives about the desired information of target slave unit (for example, HADDRN).The target slave unit information that moderator 140 uses this information and is associated is so that arbitrate action.After arbitration and checking bus availability, moderator 140 is sent to selected main equipment with effective HREADY signal, and which main equipment is actual to have bus entitlement to indicate.
Traditional, after arbitration, authorize HGRANT signal.In example embodiment of the present invention, as mentioned above, after request, still before arbitration, authorize HGRANT signal.
Fig. 6 illustrates example sequential chart of the present invention.As shown in Figure 6, in response to the HBUSREQ1 signal with the HGRANT1 signal triggering to high level.In addition, in response to of the conversion of HGRANT1 signal, generate HADDR1 signal and itself and HCLK is synchronous to high level.Similarly, in response to the HBUSREQ2 signal with the HGRANT2 signal triggering to high level.In addition, in response to of the conversion of HGRANT2 signal, generate HADDR2 signal and itself and HCLK is synchronous to high level.Equally as shown in Figure 6, generate the data message HRDATA that comprises DATA1, and generate data, particularly DATA5 in response to HREADY2 in response to the HREADY1 signal.As shown in Figure 6, according to example embodiment of the present invention, moderator 40 receives the HADDR2 signal from main equipment 110,120,130 earlier, thereby reduces time delay.
In Fig. 7 and/or 8, HADDR, HBURST, each all is the signal that drives the target slave unit for the HWRITE signal.The BIREQD signal is that the request target slave unit is the signal that data access is prepared.BIADDR, BIBA, BIRCONT, BICCONT are the signals that comprises the information of controlled target slave unit.The BICONFIRMD signal is to the affirmation of BIREQD signal (ACK) signal.NDCAS, NRAS, NCAS, NDWE signal are the command signals of access target slave unit, or are the command signal of the specific private memory memory field of access in other example embodiment.The BA signal is the memory field address signal, and the BIREADYD signal is that movable signal has been provided when the target slave unit has been ready to provide data to transmit.The HREADYN signal is that the indication specific master has now and is used for from/proprietorial the signal of bus that transmits to the data of target slave unit.
That Fig. 7 illustrates is more detailed, according to the bus structure of Fig. 5 of example embodiment of the present invention.As shown in Figure 7, moderator 550 comprises host device interface 552 and slave unit control unit interface 554.Host device interface 552 interacts with N main equipment unit 510,520,530, and slave unit control unit interface 554 interacts with M slave unit controller 571,572,573.M the one or more slave units of slave unit controller 571,572,573 controls unit 541,542,543.
As shown in Figure 7, each main equipment unit 510,520,530 provides a HBUSREQ signal to moderator 550.Moderator 550 generates a HGRANT signal to each main equipment unit.Each main equipment unit provides HADDR signal, HBURST signal and/or HWRITE signal to moderator 550 subsequently.
In the main equipment unit 510,520,530 each provides a HWDATAn signal to multiplexer (MUX) 560, and a selected HWDATAn signal is provided to slave unit controller 571,572,573 as BIWDATA.Slave unit controller 571,572,573 to/541,542,543 transmit data from described slave unit unit.Slave unit controller 571,572,573 also provides a BIRDATAn signal to multiplexer (MUX) 580, and provides to the main equipment unit 510,520,530 with a selected BIRDATAn signal as the BIRDATA signal.
Fig. 8 illustrates the concrete structure of the another kind of example of versabus moderator scheme shown in Figure 5.As shown in Figure 8, moderator 250 comprises host device interface 252 and sdram controller interface 254.Host device interface 252 is to interact in conjunction with the illustrated roughly the same method of Fig. 7 and main equipment unit 210,220,230 and multiplexer 260 with top.Sdram controller interface 254 provides BIREQD, BIADDR, BIBA, BIBE, BIRCONT and BICCONT signal to sdram controller 270, and receives BIREADYD and BICONFIRMD signal from sdram controller 270.Sdram controller receives BIWDATA selected, MUX260 in the autonomous device unit 210,220,230, and provides to the main equipment unit 210,220,230 selected one with BIRDATA.Sdram controller 270 is NDCS, NRAS, and NCAS, NDWE, BA and ADDR signal provide to SDRAM240, and receive the data of returning from SDRAM240.In example embodiment, SDRAM240 comprises one or more store memories district, is denoted as unit 241,242,243 and 244.
Fig. 9 illustrates according to exemplary sequential chart of the present invention.As shown in Figure 9, because moderator allows via pseudo-grant signal to send earlier, so main equipment can send information earlier.Because moderator is the information of receiving target slave unit earlier, so moderator can be that the data transmission is prepared via RAS1 and CAS1 request signal slave unit.
Figure 10 illustrates the example embodiment of the host device interface shown in Fig. 7 or 8.As shown in Figure 10, host device interface 252,552 comprises synchronizer unit 1001,1002,1003, and each in the described synchronizer unit receives the HBUSREQ signal and exports the HGRANT signal from the main equipment unit.Host device interface 252,552 also comprises multiplexer (MUX) 1005,1006,1008, and described multiplexer receives the indicating target slave unit and has been ready for sending the BIREADYD signal of data, and exports one or more HREADY signals.As shown in Figure 10, host device interface 252,552 does not need to comprise any arbitrated logic.
Figure 11 illustrates process flow diagram according to one example embodiment.Shown in step 310, moderator determines whether that at least one main equipment asking bus access.If not, then moderator rests on and keeps circulation.If then at step S320, moderator is sent to all request main equipment unit with the HGRANT signal.At step S330, moderator receives drive signal from all request main equipment unit.In step 340,, select specific main equipment by moderator based on the status information of bus driver information and target slave unit.
At step S350, do not consider bus availability in order to reduce the time delay that is associated with the target slave unit, the moderator request is that the data transmission is prepared by the target slave unit of selected main equipment access.At step S360, the slave unit controller sends command signal to the target slave unit.Process flow diagram shown in Figure 11 can be considered to the phase one of exemplary method of the present invention.
Figure 12 illustrates subordinate phase, and wherein in step 410, moderator determines whether that arbitrary target slave unit finished the preparation that data transmit.If not, then moderator rests on and keeps circulation.If then in step 420, moderator determines whether bus is available.If bus is unavailable, then moderator rests on and keeps circulation.If bus can be used, then in step 430, moderator is selected one and is attempted the request main equipment that the target slave unit of data transmission preparations has been finished in access.In step 440, between selected bus master and the target slave unit that is associated, transmit data, and repeat this process.
As mentioned above, example embodiment of the present invention has been revised the order of arbitrating signals from traditional order.Especially, in example embodiment, pseudo-grant signal is before arbitration.In addition, in example embodiment, information is transmitted in before the arbitration, thereby can use the information that comprises in data transmit in arbitration.Owing to can use additional information, example embodiment of the present invention has reduced or eliminated stand-by period T and/or has enabled arbitration preferably.
Although example embodiment of the present invention has been described specific control unit interface and storer, will understand that as the those of ordinary skill of this area, can use any other interface and/or storer.Further, although example embodiment of the present invention has been described specific bus conflict, will understand that as the those of ordinary skill of this area the present invention also can be used to solve any other bus conflict, or any other contention for resources.
Even now has been described the present invention, but obviously can change the present invention in many kinds of modes.Not such variation as being to the running counter to of the spirit and scope of the present invention, and attempt the modification as for obvious all of a those of ordinary skill of this area is included within the scope of claim subsequently.
Claims (33)
1. the moderator in the system is used for generating pseudo-grant signal to all request main equipment unit, and is used for receiving transaction information in response to this pseudo-grant signal from all request main equipment unit.
2. moderator as claimed in claim 1, this moderator are also arbitrated based on the transaction information that receives from request main equipment unit.
3. moderator as claimed in claim 1, this moderator comprises host device interface, is used for generating pseudo-grant signal to all request main equipment unit; Be used for receiving transaction message from all request main equipment unit in response to pseudo-grant signal; Generate ready signal with being used for to a selected request main equipment unit.
4. moderator as claimed in claim 3, described host device interface comprises at least one maker, is used for generating pseudo-grant signal from least one request signal from all request main equipment unit.
5. moderator as claimed in claim 3, described host device interface comprises at least one circuit, is used for converting the target slave unit ready signal from least one slave unit to be used for a selected request main equipment unit data and transmits ready signal.
6. moderator as claimed in claim 3, wherein said ready signal are used for data and transmit.
7. moderator as claimed in claim 3, wherein said ready signal indication bus availability.
8. moderator as claimed in claim 1, described moderator comprise a control unit interface, and being used in response to come at least one slave unit unit of requirement from the target information of a selected request main equipment unit is that the data transmission is prepared.
9. moderator as claimed in claim 8, wherein said control unit interface are the slave unit control unit interfaces, and at least one slave unit controller of this interface and at least one slave unit unit interacts.
10. moderator as claimed in claim 9, wherein each slave unit controller is controlled at least one slave unit storer.
11. moderator as claimed in claim 8, wherein said control unit interface are the sdram controller interfaces, at least one sdram controller of this interface and at least one slave unit unit interacts.
12. as the moderator that claim 11 is stated, wherein each sdram controller is controlled at least one SDRAM store memory district.
13. moderator as claimed in claim 1 is wherein synchronous from the request and the system clock of all request main equipment unit.
14. a system comprises:
At least one is used to the main equipment unit of the request that generates;
Moderator is used for from least one main equipment unit reception described request, and is used for generating pseudo-grant signal in response to the request from least one main equipment unit;
At least one provides the main equipment unit of target information to moderator in response to pseudo-grant signal; With
At least one is that data transmit the slave unit unit of preparing in response to the target information that is provided by described at least one main equipment unit.
15. system as claimed in claim 14, the preparation that data transmit is finished in wherein said at least one slave unit unit, and data transmit between one of one of at least one main equipment unit and at least one slave unit unit.
16. system as claimed in claim 14, wherein all request main equipment unit receive pseudo-grant signal from moderator in the system.
17. system as claimed in claim 14 is wherein synchronous from the request and the system clock of described at least one main equipment unit.
18. system as claimed in claim 14 is synchronous from the pseudo-grant signal of moderator with target information from least one main equipment unit wherein.
19. a method of arbitrating in system comprises step:
Generate pseudo-grant signal in response to request, and
In response to described pseudo-grant signal receiving target information.
20. method as claimed in claim 19 also comprises step:
Arbitrate based on described target information.
21. method as claimed in claim 19, wherein said request and target information come from a plurality of main equipments unit.
22. method as claimed in claim 19 wherein generates pseudo-grant signal in response to all requests.
23. method as claimed in claim 19 also comprises step:
Ask to prepare in response to target information for data transmit.
24. method as claimed in claim 19, wherein said request and system clock are synchronous.
25. method as claimed in claim 19, wherein this method is a software or hard-wired.
26. a method of arbitrating in system comprises:
Generate request;
Receive described request and generate pseudo-grant signal in response to this request;
Provide target information in response to described pseudo-grant signal; With
Come to prepare in response to described target information for data transmit.
27. method as claimed in claim 26, wherein said request and target information come from a plurality of request main equipments unit.
28. method as claimed in claim 27 also comprises step:
Finish the data transmission preparations; With
Transmit data.
29. method as claimed in claim 26, receives, provides and prepare to form the phase one at wherein said generation, describedly finishes and transmit the composition subordinate phase, and first and second stages took place simultaneously.
30. method as claimed in claim 29 is wherein saidly finished the data transmission preparations and is comprised: determine that bus is whether available and select in the main equipment of request one.
31. method as claimed in claim 26 wherein generates described pseudo-grant signal in response to all requests.
32. method as claimed in claim 26, wherein said request and system clock are synchronous.
33. method as claimed in claim 26, wherein said method are software or hard-wired.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR33048/2003 | 2003-05-23 | ||
| KR1020030033048A KR100626362B1 (en) | 2003-05-23 | 2003-05-23 | Arbiter and method for arbitrating high-performance bandwidth system bus and bus system having arbiter |
| KR33048/03 | 2003-05-23 | ||
| US10/737,124 US8209453B2 (en) | 2003-05-23 | 2003-12-17 | Arbiter, a system and a method for generating a pseudo-grant signal |
| US10/737,124 | 2003-12-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1573721A true CN1573721A (en) | 2005-02-02 |
| CN100419722C CN100419722C (en) | 2008-09-17 |
Family
ID=33422295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100459127A Active CN100419722C (en) | 2003-05-23 | 2004-05-24 | Arbiter, a system and a method for generating a pseudo-grant signal |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4684577B2 (en) |
| CN (1) | CN100419722C (en) |
| DE (1) | DE102004024849B4 (en) |
| FR (1) | FR2855285B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105993007A (en) * | 2013-11-25 | 2016-10-05 | 高通股份有限公司 | Multipoint interface shortest pulse width priority resolution |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100726101B1 (en) * | 2005-04-29 | 2007-06-12 | (주)씨앤에스 테크놀로지 | System for Controlling Memory |
| KR101153712B1 (en) * | 2005-09-27 | 2012-07-03 | 삼성전자주식회사 | Apparatus and method for access controlling multi-port SDRAM |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6195469A (en) * | 1984-10-16 | 1986-05-14 | Fujitsu Ltd | Competition control system of multiprocessor |
| JPS61210463A (en) * | 1985-03-14 | 1986-09-18 | Fujitsu Ltd | Data transfer control system |
| US4947368A (en) * | 1987-05-01 | 1990-08-07 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
| US6073199A (en) * | 1997-10-06 | 2000-06-06 | Cisco Technology, Inc. | History-based bus arbitration with hidden re-arbitration during wait cycles |
| US6393506B1 (en) * | 1999-06-15 | 2002-05-21 | National Semiconductor Corporation | Virtual channel bus and system architecture |
| US6718422B1 (en) * | 1999-07-29 | 2004-04-06 | International Business Machines Corporation | Enhanced bus arbiter utilizing variable priority and fairness |
| CN100445973C (en) * | 2002-04-17 | 2008-12-24 | 威盛电子股份有限公司 | Method for arbitrating bus control right and its arbitrator |
-
2004
- 2004-05-13 DE DE200410024849 patent/DE102004024849B4/en not_active Expired - Lifetime
- 2004-05-19 FR FR0405490A patent/FR2855285B1/en not_active Expired - Fee Related
- 2004-05-24 JP JP2004152664A patent/JP4684577B2/en active Active
- 2004-05-24 CN CNB2004100459127A patent/CN100419722C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105993007A (en) * | 2013-11-25 | 2016-10-05 | 高通股份有限公司 | Multipoint interface shortest pulse width priority resolution |
| CN105993007B (en) * | 2013-11-25 | 2019-06-25 | 高通股份有限公司 | The parsing of multipoint interface most short pulse duration priority |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100419722C (en) | 2008-09-17 |
| JP4684577B2 (en) | 2011-05-18 |
| DE102004024849B4 (en) | 2008-11-27 |
| FR2855285B1 (en) | 2006-07-07 |
| DE102004024849A1 (en) | 2004-12-23 |
| FR2855285A1 (en) | 2004-11-26 |
| JP2004348745A (en) | 2004-12-09 |
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