FR2854495A1 - Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille. - Google Patents

Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille.

Info

Publication number
FR2854495A1
FR2854495A1 FR0305263A FR0305263A FR2854495A1 FR 2854495 A1 FR2854495 A1 FR 2854495A1 FR 0305263 A FR0305263 A FR 0305263A FR 0305263 A FR0305263 A FR 0305263A FR 2854495 A1 FR2854495 A1 FR 2854495A1
Authority
FR
France
Prior art keywords
grid
cavity
integrated circuit
filling material
injection mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR0305263A
Other languages
English (en)
Other versions
FR2854495B1 (fr
Inventor
Jean Luc Diot
Jerome Teysseyre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0305263A priority Critical patent/FR2854495B1/fr
Priority to US10/827,612 priority patent/US7358598B2/en
Publication of FR2854495A1 publication Critical patent/FR2854495A1/fr
Application granted granted Critical
Publication of FR2854495B1 publication Critical patent/FR2854495B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Procédé de fabrication d'un boîtier semi-conducteur et boîtier semi-conducteur, dans lesquels une grille métallique plate comprend des parties espacées dont au moins certaines constituent des pattes de connexion électrique, une puce de circuits intégrés fixée en avant de cette grille, des moyens de connexion électrique reliant électriquement ladite puce auxdites pattes de connexion électrique et des moyens d'encapsulation de cette puce en avant de la grille, et dans lesquels une plaque (18) est constituée de ladite grille (1) et d'une matière de remplissage (17) qui remplit les espaces séparant lesdites parties espacées de cette grille et lesdits moyens d'encapsulation (27, 29) sont rapportés en avant de ladite plaque (18).
FR0305263A 2003-04-29 2003-04-29 Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille. Expired - Fee Related FR2854495B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0305263A FR2854495B1 (fr) 2003-04-29 2003-04-29 Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille.
US10/827,612 US7358598B2 (en) 2003-04-29 2004-04-19 Process for fabricating a semiconductor package and semiconductor package with leadframe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0305263A FR2854495B1 (fr) 2003-04-29 2003-04-29 Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille.

Publications (2)

Publication Number Publication Date
FR2854495A1 true FR2854495A1 (fr) 2004-11-05
FR2854495B1 FR2854495B1 (fr) 2005-12-02

Family

ID=33155531

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0305263A Expired - Fee Related FR2854495B1 (fr) 2003-04-29 2003-04-29 Procede de fabrication d'un boitier semi-conducteur et boitier semi-conducteur a grille.

Country Status (2)

Country Link
US (1) US7358598B2 (fr)
FR (1) FR2854495B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI313943B (en) * 2006-10-24 2009-08-21 Chipmos Technologies Inc Light emitting chip package and manufacturing thereof
CN101241890B (zh) * 2007-02-06 2012-05-23 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
CN100539054C (zh) * 2007-03-13 2009-09-09 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
DE102008024704A1 (de) * 2008-04-17 2009-10-29 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil und Verfahren zur Herstellung eines optoelektronischen Bauteils
US9824958B2 (en) * 2013-03-05 2017-11-21 Infineon Technologies Austria Ag Chip carrier structure, chip package and method of manufacturing the same
ES2781971T3 (es) * 2013-06-28 2020-09-09 Lumileds Holding Bv Dispositivo diodo emisor de luz
DE102014213217A1 (de) * 2014-07-08 2016-01-14 Continental Teves Ag & Co. Ohg Körperschallentkopplung an mit Geberfeldern arbeitenden Sensoren

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291546A (ja) * 1992-04-08 1993-11-05 Sanyo Electric Co Ltd 固体撮像素子の製造方法
JPH05343655A (ja) * 1992-04-01 1993-12-24 Nec Corp 固体撮像装置
JPH06349870A (ja) * 1993-06-08 1994-12-22 Nec Corp 半導体装置及びその製造方法
JPH09102580A (ja) * 1995-08-02 1997-04-15 Matsushita Electron Corp 樹脂封止型半導体装置およびその製造方法
US5821532A (en) * 1997-06-16 1998-10-13 Eastman Kodak Company Imager package substrate
US20020093026A1 (en) * 2001-01-17 2002-07-18 Chien-Ping Huang Image sensor of a quad flat package

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Publication number Priority date Publication date Assignee Title
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
JP3614776B2 (ja) * 2000-12-19 2005-01-26 シャープ株式会社 チップ部品型ｌｅｄとその製造方法
JP4637380B2 (ja) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
DE10148120B4 (de) * 2001-09-28 2007-02-01 Infineon Technologies Ag Elektronische Bauteile mit Halbleiterchips und ein Systemträger mit Bauteilpositionen sowie Verfahren zur Herstellung eines Systemträgers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343655A (ja) * 1992-04-01 1993-12-24 Nec Corp 固体撮像装置
JPH05291546A (ja) * 1992-04-08 1993-11-05 Sanyo Electric Co Ltd 固体撮像素子の製造方法
JPH06349870A (ja) * 1993-06-08 1994-12-22 Nec Corp 半導体装置及びその製造方法
JPH09102580A (ja) * 1995-08-02 1997-04-15 Matsushita Electron Corp 樹脂封止型半導体装置およびその製造方法
US5821532A (en) * 1997-06-16 1998-10-13 Eastman Kodak Company Imager package substrate
US20020093026A1 (en) * 2001-01-17 2002-07-18 Chien-Ping Huang Image sensor of a quad flat package

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0180, no. 80 (E - 1505) 9 February 1994 (1994-02-09) *
PATENT ABSTRACTS OF JAPAN vol. 0181, no. 71 (E - 1529) 23 March 1994 (1994-03-23) *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 03 28 April 1995 (1995-04-28) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 08 29 August 1997 (1997-08-29) *

Also Published As

Publication number Publication date
US7358598B2 (en) 2008-04-15
US20050017330A1 (en) 2005-01-27
FR2854495B1 (fr) 2005-12-02

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