FR2821208B1 - Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille - Google Patents

Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille

Info

Publication number
FR2821208B1
FR2821208B1 FR0102347A FR0102347A FR2821208B1 FR 2821208 B1 FR2821208 B1 FR 2821208B1 FR 0102347 A FR0102347 A FR 0102347A FR 0102347 A FR0102347 A FR 0102347A FR 2821208 B1 FR2821208 B1 FR 2821208B1
Authority
FR
France
Prior art keywords
dielectric
grid
realizing
interconnection level
intermediate interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0102347A
Other languages
English (en)
Other versions
FR2821208A1 (fr
Inventor
Philippe Coronel
Francois Leverd
Paul Ferreira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0102347A priority Critical patent/FR2821208B1/fr
Priority to US10/081,296 priority patent/US6689655B2/en
Publication of FR2821208A1 publication Critical patent/FR2821208A1/fr
Application granted granted Critical
Publication of FR2821208B1 publication Critical patent/FR2821208B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
FR0102347A 2001-02-21 2001-02-21 Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille Expired - Fee Related FR2821208B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0102347A FR2821208B1 (fr) 2001-02-21 2001-02-21 Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille
US10/081,296 US6689655B2 (en) 2001-02-21 2002-02-20 Method for production process for the local interconnection level using a dielectric conducting pair on pair

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0102347A FR2821208B1 (fr) 2001-02-21 2001-02-21 Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille

Publications (2)

Publication Number Publication Date
FR2821208A1 FR2821208A1 (fr) 2002-08-23
FR2821208B1 true FR2821208B1 (fr) 2003-04-11

Family

ID=8860269

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0102347A Expired - Fee Related FR2821208B1 (fr) 2001-02-21 2001-02-21 Procede de realisation du niveau d'interconnexion intermediaire utilisant le couple dielectrique-conducteur sur grille

Country Status (2)

Country Link
US (1) US6689655B2 (fr)
FR (1) FR2821208B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004835A (en) * 1997-04-25 1999-12-21 Micron Technology, Inc. Method of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to anode location and an electrical interconnection with a transistor source/drain region
US7045073B2 (en) * 2002-12-18 2006-05-16 Intel Corporation Pre-etch implantation damage for the removal of thin film layers
FR2890234A1 (fr) * 2005-08-29 2007-03-02 St Microelectronics Crolles 2 Procede de protection de la grille d'un transistor et circuit integre correspondant
US7595248B2 (en) * 2005-12-01 2009-09-29 Intel Corporation Angled implantation for removal of thin film layers
US7648869B2 (en) * 2006-01-12 2010-01-19 International Business Machines Corporation Method of fabricating semiconductor structures for latch-up suppression
US20070158779A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried damage layer
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US7276768B2 (en) * 2006-01-26 2007-10-02 International Business Machines Corporation Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
US20070194403A1 (en) * 2006-02-23 2007-08-23 International Business Machines Corporation Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
US7754513B2 (en) * 2007-02-28 2010-07-13 International Business Machines Corporation Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213990A (en) * 1992-04-01 1993-05-25 Texas Instruments, Incorporated Method for forming a stacked semiconductor structure
US5340774A (en) * 1993-02-04 1994-08-23 Paradigm Technology, Inc. Semiconductor fabrication technique using local planarization with self-aligned transistors
JP2833407B2 (ja) * 1993-03-24 1998-12-09 日本ゼオン株式会社 新規油吸着材組成物
FR2752644B1 (fr) * 1996-08-21 1998-10-02 Commissariat Energie Atomique Procede de realisation d'un transistor a contacts auto-alignes
JP3554514B2 (ja) * 1999-12-03 2004-08-18 松下電器産業株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
FR2821208A1 (fr) 2002-08-23
US20020142519A1 (en) 2002-10-03
US6689655B2 (en) 2004-02-10

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20071030