FR2805369B1 - Structure de registre avec un mecanisme d'ecriture symetrique - Google Patents
Structure de registre avec un mecanisme d'ecriture symetriqueInfo
- Publication number
- FR2805369B1 FR2805369B1 FR0012723A FR0012723A FR2805369B1 FR 2805369 B1 FR2805369 B1 FR 2805369B1 FR 0012723 A FR0012723 A FR 0012723A FR 0012723 A FR0012723 A FR 0012723A FR 2805369 B1 FR2805369 B1 FR 2805369B1
- Authority
- FR
- France
- Prior art keywords
- writing mechanism
- register structure
- symmetric
- symmetric writing
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/507,207 US6226217B1 (en) | 2000-02-18 | 2000-02-18 | Register structure with a dual-ended write mechanism |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2805369A1 FR2805369A1 (fr) | 2001-08-24 |
| FR2805369B1 true FR2805369B1 (fr) | 2002-10-18 |
Family
ID=24017673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0012723A Expired - Fee Related FR2805369B1 (fr) | 2000-02-18 | 2000-10-05 | Structure de registre avec un mecanisme d'ecriture symetrique |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6226217B1 (fr) |
| FR (1) | FR2805369B1 (fr) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6832277B2 (en) | 2001-08-02 | 2004-12-14 | Sun Microsystems, Inc. | Method and apparatus for transmitting data that utilizes delay elements to reduce capacitive coupling |
| US20040053510A1 (en) * | 2002-09-16 | 2004-03-18 | Little Casey J. | System for and method of unlimited voltage multi ported sram cells |
| US10943648B1 (en) | 2016-12-06 | 2021-03-09 | Gsi Technology, Inc. | Ultra low VDD memory cell with ratioless write port |
| US10777262B1 (en) | 2016-12-06 | 2020-09-15 | Gsi Technology, Inc. | Read data processing circuits and methods associated memory cells |
| US10770133B1 (en) | 2016-12-06 | 2020-09-08 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
| US10847213B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
| US10521229B2 (en) | 2016-12-06 | 2019-12-31 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
| US10891076B1 (en) | 2016-12-06 | 2021-01-12 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
| US10847212B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers |
| US10860320B1 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
| US11227653B1 (en) | 2016-12-06 | 2022-01-18 | Gsi Technology, Inc. | Storage array circuits and methods for computational memory cells |
| US10998040B2 (en) | 2016-12-06 | 2021-05-04 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
| US10877731B1 (en) | 2019-06-18 | 2020-12-29 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
| US10930341B1 (en) | 2019-06-18 | 2021-02-23 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
| US10958272B2 (en) | 2019-06-18 | 2021-03-23 | Gsi Technology, Inc. | Computational memory cell and processing array device using complementary exclusive or memory cells |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734613A (en) * | 1996-06-20 | 1998-03-31 | Northern Telecom Limited | Multi-port random access memory |
| JPH117773A (ja) * | 1997-06-18 | 1999-01-12 | Sony Corp | 半導体記憶装置 |
| JPH11261017A (ja) * | 1998-03-16 | 1999-09-24 | Fujitsu Ltd | 半導体記憶装置 |
| US6104663A (en) * | 1999-01-06 | 2000-08-15 | Virage Logic Corp. | Memory array with a simultaneous read or simultaneous write ports |
| JP3698929B2 (ja) * | 1999-09-22 | 2005-09-21 | 日本電気株式会社 | 半導体記憶装置 |
-
2000
- 2000-02-18 US US09/507,207 patent/US6226217B1/en not_active Expired - Lifetime
- 2000-10-05 FR FR0012723A patent/FR2805369B1/fr not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| FR2805369A1 (fr) | 2001-08-24 |
| US6226217B1 (en) | 2001-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |
Effective date: 20090630 |