FR2787233A1 - Verifying integrity of decoding circuits of memory matrix by performing at least N or M writing of second words in storage in such way that every line and every column has at least registered second word - Google Patents

Abstract

After having written all words to a memory with a same first word (h00), it performs at least N or M writing of second words (h01 hFE) in the storage in such a way that every line and every column has at least registered second word. The second words are different from the first words. Then all words of the storage matrix are read.

Description

Method for verifying the integrity of the

decoding of a memory.

  The invention relates to a method for verifying

  the integrity of the memory decoding circuits.

  The invention relates more particularly to production tests, in particular to a test known as the diagonal test. An important step during the manufacture of an integrated circuit is the verification of the proper functioning of the circuits at the end of the production chain. Given the sizes of the transistors, it is not uncommon for an impurity deposited either on a manufacturing mask or on the silicon washer during manufacturing to cause an error on the circuit. Errors are expressed in different ways, which can be a connection fault, a short circuit, a faulty transistor. In general, this amounts to having so-called signals glued either between two signals, or

  more generally pasted at "1" or pasted at "0".

  For memories, the integration density is maximum and the risk of sticking is increased. Many tests are developed to individually test all the functional elements of memory. Since the test time should be reduced to the maximum for cost reasons, the fastest tests are carried out first, which allow a maximum of errors to be detected so that all of the tests are not

  performed only on valid components.

  One of the first tests carried out on the memories consists in verifying the integrity of the storage matrix. This matrix integrity test is one of the shortest and therefore allows rapid sorting of defective components. However, the other memory elements must also be tested. This makes it possible, among other things, to carry out all the other tests considering that the storage matrix is functioning correctly. To verify the integrity of the decoding circuits, the diagonal test is known in the state of the art. The diagonal test consists of putting all the memory cells in a first state and then writing, in a second state, all the memory cells which are located on the diagonal of the

memorization matrix.

  FIG. 1 represents a matrix 1 of cells 2 of square type storage. The content of the storage cells 2 is indicated on each cell 2. It can be seen that all of the cells contain the binary information "0" with the exception of the cells of the diagonal of

  the matrix 1 which contain the binary information "1".

  The diagonal test ends with a reading of each storage cell to verify that there is no multiple decoding of rows or columns. Multiple decoding results in an incorrect reading of the content of certain cells. Indeed, when an error occurs during the writing, two bits or none are written simultaneously instead of only one transforming a "0" into "1", or the reverse. Likewise, when a decoding error occurs during reading, several cells are read simultaneously and the information read is the result of a logical function of AND type or of OR type (depending on the type of memory and / or depending on the error)

  between the data read simultaneously.

  The diagonal test is very effective in

  case of a storage matrix of square type, that is to say

  say for a matrix that has as many rows

  (word lines) than columns (bit lines).

  However, it is frequent to have storage matrices of rectangular type, that is to say which have a different number of rows and columns. If we refer to memories with access per page (conventionally, a page is 64 words of 8 bits). This results in a memory which has 512 columns whatever its total capacity. The diagonal test is then translated as shown in Figures 2 and 3. The rectangular matrix is divided into several square matrices. As those skilled in the art can see in FIGS. 2 and 3, the written patterns are repeated for different addresses. This is all the more annoying as the pattern is repeated for addresses where only a single bit changes. It is therefore not possible to validly test the decoding concerning this single bit because changing this bit amounts to testing an identical memory area. In some cases, the memory can even be broken down into a larger number of squares (there are today memories accessible per page whose size varies between 1 kbits and 16 Mbits which results in a variable number of lines, for a fixed number of columns). In some cases, the number of repeated squares is greater and results in the non-testability of the decoding of a large number of address bits. In addition, the memories most subject to non-rectangular sizes are generally organized in words, others are even configurable according to

multiple word sizes.

  The invention proposes to improve the test technique by taking advantage of the word organization of the memory. The method proposed by the invention makes it possible on the one hand to overcome the test uncertainties described above, and on the other hand to reduce the test time. The subject of the invention is a method for verifying the integrity of the decoding circuits of a memory comprising a storage matrix comprising N lines and M columns of words of L bits, the storage matrix having N * M * L cells. memory accessible by means of N * M addresses by words of L bits, N, M and L being positive integers greater than 1, in which, after having written all the words of the memory with the same first word, performs at least N or M writing of second words in the storage matrix in such a way that each row and each column has at least one second written word, the second words being different from the first word, then

  we read all the words in the memory matrix.

  Such a method makes it possible to reduce the number of writes and to reduce the number of address bits, the decoding of which is not verifiable, by the size of the words when testing a memory having a small number of lines. . It is good to predict, if several second words are written on the same line or in the same column that the second words are different. This reduces the risk of

  non-testability of the decoding of an address bit.

  An improvement, for memories which have a writing mode per page, consists in that a plurality of different second words are written

simultaneously on the same line.

  In practical terms, the second words are written on the diagonals of memory blocks, each block having as many word lines as there are columns of words. The use of a block write algorithm makes it possible to dispense with the shape of the storage matrix. The invention will be better understood and other features and advantages will appear on reading

  the description which follows, the description making

  reference to the appended drawings among which: FIG. 1 represents a square memory and its content according to the state of the art, FIGS. 2 and 3 represent the distribution of ôrv i um test data on matrices of rectangular type,

according to the state of the art.

  Figure 4 shows a distribution of data

  test on a memory according to the invention.

  Figures 5 and 6 show two algorithms for

  progress of a test according to the invention.

  FIG. 4 represents an example of filling pattern according to the invention. Columns 3 are

  columns of. words and not bit columns.

  The use of word columns makes it possible to considerably reduce the number of writes to be carried out when the matrix has fewer rows than columns (the number of writes being divided in this case

by the size of the words).

  In FIG. 4, the person skilled in the art can notice that we write diagonals of words which may seem useless. However, if the memory is configurable in two word sizes, for example 8 and 16 bits, this amounts to writing in 16 bits, ie two words at a time, the verification reading being carried out in 8 bits. It is also possible when using memories with access per page (64 words of 8 bits) to carry out writes per page which makes it possible to carry out 4 or 8 writes (possibly more) simultaneously on each line. A person skilled in the art can see that the writes amount to testing the memory in blocks, each block using a different writing word. The choice of words is not very important but you must avoid using identical words on the same line

o on the same column.

  Many implementation algorithms are possible. FIGS. 5 and 6 represent two algorithms given by way of example which can be

implemented according to the invention.

  FIG. 5 represents a simple implementation algorithm. In this algorithm, X corresponds for example to a word column index and Y corresponds for example to a word line index. For the example illustrated in FIG. 5, it is assumed that a maximum number of YMAX lines of words is less than a maximum number

XMAX columns of words.

  During a first step 50, all of the words of the storage matrix are written with a single word, for example the eight-bit coded word h00 (the "h" signifying that it is a coded word in hexadecimal). The progress of this first step 50 can be done word by word, page by page or globally according to the

  possibilities offered by the memory to be tested.

  After the first step 50, a second step 51 is executed. During this second step 51, an eight-bit word to write, for example, is initialized at the value hO1, a column column index X of a word, for example at 0 , and

  a word line index Y, for example 0.

  Then, we enter a writing loop which begins with a first test 52. The first test 52 compares the index of column X with the maximum number of columns XMAX. If the index of column X is less than the maximum number of columns XMAX, then a second test 53 is carried out. If the index of column X is not less than the maximum number of columns XMAX, then we

performs a third step 54.

  The second test 53 compares the row index Y with the maximum number of rows YMAX. If the line index Y is less than the maximum number of lines YMAX, then a fourth step 55 is carried out. If the line index Y is not less than the maximum number of lines YMAX, then a fifth step 56 is carried out before

  perform the fourth step 55.

  The third step 54 consists in verifying the writes in the storage matrix. This third step 54i amounts to reading all the words in the storage matrix in order to verify that the reading of the content corresponds to what has been written. If the reading of all the memory is correct, then the memory is recognized valid, if not, the memory is recognized not

  operational. The third step 54 ends the test.

  In the fourth step 55, the word to be written is written to the storage location which corresponds to the word line with current index Y and to the word column

of current index X.

  During the fifth step 56, the line index Y is initialized to 0 and the word to be written is incremented

of a unit.

  After having executed the fourth step 55, a sixth step 57 is carried out. The sixth step 57 consists in updating the indices of row Y and of column X. The indices of row Y and of column are then incremented by one each. At the end of this

  sixth step, the first test 52 is carried out again.

  This simple example of implementation can undergo numerous modifications without departing from the scope of the invention. If the maximum number of YMAX rows is greater than the maximum number of XMAX columns, the row and column indices must be exchanged to have

  a writing algorithm of reduced duration.

  Likewise, the different numerical values are arbitrary. Indeed, during the first step 50, one can very well initialize the matrix with another numerical value, on condition of not using this

  numeric value as a word to write later.

  Preferably, either the value hOO or the value hFF is used for this first step since certain memories allow a setting to "1" or a setting to

  "0" 'global for all the storage bits.

  With regard to the word to be written, it was chosen in the example of FIG. 5 to initialize it with hOl then to increment it. Any other initialization value, as well as any other mode of changing the word to write other than a simple incrementation is possible. Do not write the same word twice on the same line or in the same column. During the second step 51, the row and column indices are initialized to 0. it is quite possible to use another initialization, for example Y = 3. In this case, the diagonals of square matrix will not correspond to the registered motif. Likewise, you can increment Y by three units instead of one unit, but

  the pattern will no longer correspond to diagonals.

  Preferably, the diagonals of square word blocks (as many word lines as word columns) of the storage matrix are used in order to simplify

processing algorithms.

  It is also possible to initialize the indices X and Y to the respective values XMAX and YMAX and to decrement the indices X and Y. Of course, it is also necessary to carry out the tests of the indices by them

comparing to zero.

  Also, a memory has been shown using words of eight bits, the invention is completely transposable on memories organized in words of

different sizes.

  Of course, the algorithm of Figure 5 can be improved. Indeed, if you have a memory with configurable access according to at least two different word sizes, you will have to write with words of the largest size and read the memory with words of the size smaller. In this case,

  to have a word separable into two distinct words.

  Preferably, if the memory is configurable according to two word sizes, then a separable word is used

in two complementary words.

  FIG. 6 represents an algorithm for setting in 7: I, - 1 a work using a block cutting of the memory. This algorithm is particularly interesting when the memory has a writing mode per page. In this algorithm, X corresponds for example to a word column index and Y corresponds for example to a word line index. For the example illustrated in FIG. 6, it is assumed that a maximum number of YMAX rows of words is greater than a block size (a maximum number of XMAX columns of words being a multiple of the size of

  block, for example using a coefficient eight).

  During a first step 60, all of the words of the storage matrix are written with a single word, for example the eight bit word coded hFF. The course of this first step 60 can be done according to different possibilities, as explained for

step 50.

  After the first step 60, a second step 61 is executed. During this second step 61, initial first to eighth words of eight bits are initialized, for example at the respective values hOl, h03, h07, hOF, hFE, hFC, hF8 and hFO, a word column X index, for example 0, and

  a word line index Y, for example 0.

  Then we enter a write loop which begins with a first test 62. The first test 62 compares the row index Y with the maximum number of rows YMAX. If the line index Y is less than the maximum number of lines YMAX, then a second test is performed 63. If the line index Y is not less than the maximum number of lines YMAX, then we

performs a third step 64.

  The second test 63 compares the index of column X with the block size. If the column index X is less than the block size, then a fourth step 65 is carried out. If the column index X is not less than the block size, then a fifth step 66 is carried out before d 'Carry out the fourth step 65. The third step 64 consists of checking the writes in the storage matrix. This third step 64 is identical to step 54 previously described. The third step 64 ends the test. During the fourth step 65, the first to eighth words are written to the storage locations which correspond on the one hand to the current word line of index Y and on the other hand, respectively, to the column of index word Current X, to the index word column X current added to the block size, to the index word column X current added to twice the block size, to the word column to the current index X added sum three times the block size, to the word column with the current index X added four times the block size, to the word column with the current index X added five times the block size, to the column word of current index X added six times the block size, and to the column of word of current index X added seven times the block size. Obviously if the memory has a writing mode per page, this amounts to performing only one page writing. If the memory does not have a writing mode per page, writing several blocks can correspond to a waste of time, especially if the maximum number of lines of YMAX words is greater than the maximum number of

XMAX word columns.

  During the fifth step 66, the column index X is initialized to 0 and the first to eighth words are changed. The first to eighth words can be changed in different ways, for example by shifting one bit of each word. What matters in changing words is, on the one hand, to change each of the first to eighth words so that, on the one hand, the eight words are different from each other, and on the other hand, each of the first to eighth words have not been used previously, and

  respectively, as first to eighth words.

  Preferably, a word is not used more than once in a matrix. After having carried out the fourth step 65, a sixth step 67 is carried out. The sixth step 67 consists in updating the indices of row Y and of column X. The indices of row Y and of column are then incremented by one each. At the end of this

  sixth step, the first test 62 is carried out again.

  This example of implementation can undergo numerous modifications without departing from the scope of the invention. In particular, all the indications of modifications presented for the algorithm of FIG. 5 are valid for the algorithm of FIG. 6. Those skilled in the art can note that if the algorithm of FIG. 6 is carried out with a size of block equal to XMAX and if one uses only one word to write then one finds oneself in the situation of the algorithm of figure 5, in

  having the rows and columns of words reversed.

  By analogy also, if one has a memory having an access with several sizes of words and no writing mode per page, one can carry out the algorithm of figure 6 by taking as number of words to write the ratio between the largest and the smallest word size, the block size resulting from the division of the number of words of minimum size being

  on the same line divided by the number of words to write.

Claims (9)

  1. Method for verifying the integrity of the decoding circuits of a memory comprising a storage matrix comprising N rows and M columns of words of L bits, the storage matrix having N * M * L storage cells accessible to the using N * M addresses by words of L bits, N, M and L being positive integers greater than 1, characterized in that, after having written all the words in the memory with the same first word (hOO), we perform at least N or M writes of second words (hOl to hFE) in the storage matrix so that each row and each column has at least one second written word, the second words being different from the first word, then we   reads all the words from the memory matrix.   2. Method according to claim 1, characterized in that, if several second words are written on the same line or in the same column, then the second words are different.   3. Method according to one of claims 1 or 2,   the memory having a data access according to at least two word sizes, characterized in that the second words are written with the largest word size, and in that the words with the size are read of word la smaller.   4. Method according to claim 3, the memory having a data access according to only two word sizes, characterized in that the second written words of the largest size can be separated into two words of the smallest complementary size one of the other.   5. Method according to one of claims 1 to 4, the memory having a writing mode per page, characterized in that a plurality of second words   different are written simultaneously on the same line.   6. Method according to one of claims 1 to 5,   characterized in that the first word is a word made up   bits that are all in the same state.   7. Method according to claim 6, characterized in that the writing of the memory with the first word is carried out either by a setting to "1" overall, or by a setting to "0" overall of all the elementary cells of memorization.   8. Method according to one of claims 1 to 7,   characterized in that the second words are written on the diagonals of memory blocks, each block having as many word lines as there are columns of words.   9. Method according to one of claims 1 to 8,   characterized in that if N is greater than M, then N writes are performed, and in that if M is   greater than N, then M writes are performed.