FR2785479A1 - Asynchronous transmission network digital word loss processing method having block packets input identified and path route determining with output port memorizing/identifying corrupted blocks. - Google Patents

Abstract

The digital word loss processing method is applied to a network with different protocols. There is a first input port (PE) identifying (RBD,ADCB) the packet block. An indicator structure finds the sub assembly block structure. An identifier block determines path routing. An output port (PS) has detectors (GBP,FSC) memorizing each corrupted block, and identifying the corrupted blocks.

Description

Device for managing data loss in a network for switching packets or data cells. asynchronous transfer mode
The invention relates to a device for managing data loss in a packet or cell switching network with asynchronous transfer mode. Such a network includes input ports, switching elements, and output ports. Each of these means is capable of sometimes losing a data packet, either due to the possible containment of an excessive number of packets intended for the same output port, or following a fault affecting a packet.

 Such a network establishes connections between terminals to support various services such as telephony and video transmission. The signals of these different services are not affected in the same way by packet loss.

For certain services, such as video transmission, the data packets are in fact subsets of data blocks such that each data block corresponds to a unit of information specific to the service considered: For example, a frame for a video transmission service.

 When a data packet belongs to a connection supporting a telephone communication, the loss of this packet has no effect on the other packets of this telephone communication because the data of the successive packets are independent. On the other hand, the loss of a single data packet belonging to a data block corresponding to a video frame can have the consequence of degrading to a large extent the reproduction of this video frame because certain methods of video coding and decoding make it necessary the presence of all the packets in a block to correctly reproduce a video frame.

In the latter case, the loss of a data packet is almost as serious, for the quality of the transmission of a video frame, as the loss of all the packets of the corresponding block, since the loss of a data packet false the decoding of all the other packets in the block. Since packet losses are generally non-consecutive, the number of degraded video frames is almost equal to the number of lost packets. The reproduction of video images can therefore be very disturbed even if the proportion of lost packets remains low. This observation naturally incites to deliberately eliminate the following packets from a block of data disturbed by the loss of one of its packets, in order to free the network resources of the following packets whose transfer is useless.

A known method for managing the elimination of the following packets belonging to a packet disturbed by the loss of a packet consists in:
-detect, for each block transported by this network, if at least one packet of this block has already been lost by the network, with the exception of the last packet of this block;
and, when it has been detected that at least one packet has been lost in a block, eliminate all the packets following the lost packet, and belonging to the same block, at least until the penultimate packet in the block.

 This known method therefore makes it possible to concentrate eliminations on the packets belonging to the same block, when they are packets which are subsets of data blocks comprising several packets.

For its implementation, it is necessary to distinguish several types of switching network:
-For networks with buffers only in the input ports, packet losses due to traffic overload in buffers can only occur in the input ports. If we only want to manage the data losses due to such traffic overloads (therefore not those due to faults which, they, can occur elsewhere than in the ports of entry), the implementation is then simple because all the means required for the selective elimination of packets belonging to a block disturbed by the loss of at least one packet are concentrated in each input port. The means required locally are: means for identifying each block and detecting each packet belonging to this block, means for memorizing the identity of each block disturbed by the loss of one of its packets, and means for detecting and eliminating the packets following the lost packet and belonging to the block disturbed by the loss of the lost packet.

-For networks comprising buffer memories in the output ports, possibly in the input ports, and possibly in the switching elements, it is possible to split the implementation into two parts:
- on the one hand, possibly manage packet losses locally
in the ports of entry by the means indicated above;
--and on the other hand, manage packet losses in the output ports,
and possibly in the switching elements.

 This second part of the implementation is the most delicate taking into account the existence of different types of protocol for adapting data blocks to the asynchronous transfer mode, and of different types of asynchronous switching network.

For example, in the case of the asynchronous transfer mode of ATM cells, the adaptation protocol to the ATM layer called AALS consists in transmitting in series all the cells constituting a data block, it is therefore possible to delimit a block by detecting the cell at the start of the block as being the first cell received and by locating the cell at the end of the block by a characteristic indicator for the last cell. The identification of the block to which a cell belongs is therefore implicit. On the other hand, the adaptation protocols called AAL3 and AAL4 make it possible to transmit the cells constituting a data block by interleaving these cells with other cells belonging to other data blocks (called MID in these protocols
AAL3 and AAL4) in addition to the first and last cell indications.

 In a single-route routing switching network all packets follow the same path for a given connection, and they arrive at the output ports in the order in which they were received by the network. In a multi-route routing switching network, packets do not follow a single path for a given connection; and, in certain types of implementation, they do not always arrive at the output ports in the order in which they were received by the network.

 The object of the invention is to propose a management device making it possible to manage data losses satisfactorily for the quality of the services structured in data blocks; and which is compatible with all the types of protocol for adapting data blocks to the asynchronous transfer mode, and compatible with all the types of asynchronous packet (or cellute) switching network, with single-path or multi-path routing.

The object of the invention is a device for managing data loss in a data packet switching network, with asynchronous transfer mode; each packet can be a subset of a data block transmitted over a connection; each block being divided into a series of packets according to a data block adaptation protocol to the asynchronous packet transfer mode, each connection being able to use a different adaptation protocol; and this network comprising input ports and output ports interconnected by at least one switching element, for transferring each packet from an input port to at least one output port; the output ports and the switching elements being liable to lose a packet;
characterized in that it:
-first means located at the ports of entry to identify, for each
connection, each packet belonging to a block and associate with this packet:
--a structure indicator indicating that this package is a sub
set of a block cut into a series of blocks,
--and a block identifier, internal, independent of the protocol
adapter used by the connection carrying the block consi
déré,
-second means located at least at the exit ports for:
- memorize a so-called disturbed block identity, for each block which is
disturbed by the loss, at least in these output ports, of at least one
package belonging to this block; this block identity:
--- the identifier of this block,
--- and a connection identifier identifying the connection which
routes this block;
- detect, among the packets received by these second means, each
package whose structure flag indicates that this package belongs to
a block, and whose block identifier and connection identifier
correspond to a disturbed block identity which is stored;
--and eliminate at least some of the packets thus detected.

 The device thus characterized is compatible with all types of adaptation protocol because the first means, which are associated with the input ports, allow the rest of the device to operate according to a process which is constant whatever the protocol of adaptation. In fact, they associate with each packet which belongs to a block an internal block identifier which will be used by the rest of the device, and which is independent of the external adaptation protocol which was used to cut and transport this block. This block identifier and the connection identifier (conventionally present in each packet) make it possible to constitute an identity identifying the block, in particular in the case where this block is disturbed by the loss of one of its packets.

 The second means, located at least at the output ports, memorize at least the identities of the disturbed blocks at the output ports.

This memorization then makes it possible to eliminate, at least at the output ports, all the packets following the lost packet and belonging to a block already disturbed by the loss, at least at the output ports, of at least one packet .

 The device is also compatible with all types of asynchronous packet switching network because, even in the case of a network with multipath routing, it makes it possible to detect and eliminate, at least at the level of a communication port. recipient output, packets belonging to a disturbed block.

 A first preferred embodiment, specific for a network in which all the packets belonging to the same block follow the same path (single-route routing), is characterized in that the switching elements liable to lose a packet comprise third means having functions similar to those of the second means.

 The device thus characterized makes it possible to detect and manage packet losses in the switching elements as in the output ports, and therefore makes it possible to identify all the packet losses occurring beyond the input ports, and therefore to eliminate more unnecessary packages.

A second preferred embodiment, specifically designed for a network in which all the packets belonging to the same block do not necessarily follow the same path (multi-route routing), and in which the output ports do not necessarily receive packets from a block in the order in which they were received by the input ports, is characterized in that the switching elements liable to lose a packet include means for transmitting a packet known as packet loss signaling, when packet is lost in this element, at least when the structure indicator which is associated with this lost packet indicates that it belongs to a data block; this packet loss signaling packet being routed to the destination output port (s) using the same routing data (generally a self-routing label) as those routing the lost packet; and this packet loss signaling packet containing the identifier of this connection and the block identifier of the lost packet;
and in that the second means in the output ports further comprise:
means for detecting the reception of a packet signaling packet loss;
and means for memorizing the identity of a disturbed block, also when a packet signaling packet loss is received.

 The device thus characterized makes it possible to detect packet losses in the switching elements as in the output ports, and to manage them in the output ports. It therefore makes it possible to identify all the packet losses occurring beyond the input ports, and therefore to eliminate a greater number of unnecessary packets.

The invention will be better understood and other characteristics will appear with the aid of the description below and the accompanying figures:
FIG. 1 represents the block diagram of a single-route routing switching network, provided with the device according to the invention,
FIG. 2 represents the block diagram of a switching network with multi-route routing, provided with the device according to the invention,
FIG. 3 represents the block diagram of an input port of a conventional switching network, that is to say without the management device according to the invention;
FIG. 4 represents the block diagram of an input port of a switching network provided with the device according to the invention;
FIG. 5 represents the block diagram of an output port of a conventional switching network;
FIG. 6 represents the block diagram of an output port of a single-route routing switching network, provided with the device according to the invention;
FIG. 7 represents the more detailed block diagram of part of the device according to the invention in the output port shown in FIG. 6;
FIG. 8 represents the block diagram of an output port of a switching network with multi-route routing, provided with the device according to the invention;
FIG. 9 represents the more detailed block diagram of part of the device according to the invention in the output port represented in FIG. 8,
FIG. 10 represents the block diagram of a switching element of a conventional switching network;
FIG. 11 represents the block diagram of a switching element of a switching network with single-path routing, provided with the device according to the invention;
FIG. 12 represents the block diagram of a switching element of a switching network with multi-route routing provided with the device according to the invention;
FIG. 13 represents a flow diagram of the operations carried out by the device according to the invention, in the example shown in FIG. 11,
FIG. 14 represents a flow diagram of the operations carried out by the device according to the invention, in the example represented in FIG. 12.

 The network examples described in the following are switching networks conveying data organized in cells with asynchronous transfer mode, but the invention is also applicable to any other type of network conveying data packets according to an asynchronous transfer mode. .

Figure 1 shows the block diagram of a switching network
SPSN with single-route routing, provided with the device according to the invention. II:
-m inputs E1, ..., Em each receiving a series of cells;
-n outputs S1, ..., Sn;
-m input ports PE'1, ..., PE'm, each having an input constituting res
one of the network inputs E1, ..., Em, one input port PE '
being shown, by way of example;
-n output ports, PS'1, ..., PS'n, each having an output constituting one
outputs S1, ..., Sn of the network, a single output port PS 'being represented, at ti
be an example;
-a plurality of switching elements arranged in one or more stages
between the input and output ports, a single switching element
EC being shown, by way of example.

 The block diagram of a PE's input port will be described in more detail below, with reference to FIG. 4. The block diagram of a PS's output port will be described in more detail below, with reference in Figure 6. The block diagram of an EC's switching element will be described in more detail below, with reference to Figure 11.

Each PE input port identifies, for each connection and for each
cell, its membership of a block, and associates with this cell:
--a structure indicator indicating whether this cell is a sub
set of a block cut into a series of blocks,
--and if so, a block identifier, internal, independent of the
external adaptation protocol used for the connection to which ap
the block considered, and which can be provided by a management circuit
free block identifiers.

 Each output port PS eliminates the cells according to a lost cell, and belonging to the same block as this lost cell, except for the last cell possibly. The SPSN network being of the single-path type, all the cells constituting the same block necessarily pass through the same switching element EC 'in a given intermediate stage. An EC 'switching element of an intermediate stage eliminates additional cells, based on the fact that it can detect a cell belonging to a block already disturbed by the loss of a cell in this same EC switching element .

Figure 2 shows the block diagram of a switching network
MPSN with multi-route routing, provided with the device according to the invention. II:
-m inputs E1, ..., Em each receiving a series of cells;
-n outputs S1, ..., Sn;
-m input ports PE'1, ..., PE'm each having an input constituting res
one of the network inputs E1, ..., Em, one input port PE '
being shown, by way of example;
-n output ports, Pus1 ", .., PS" n, each having an output constituting one
outputs S1, ..., Sn of the network, a single output port PS "being represented, at ti
be an example;
-a plurality of EC switching elements "arranged in one or more
stages between the input ports and the output ports, a single EC element "being
shown, by way of example.

 The block diagram of an input port PE 'of this network with multi-route routing is identical to that of a port PE' of the network with single-route routing represented in FIG. 1. It has the same functions and will be described in more detail detail below, referring to figure 4. The block diagram of a PS "output port will be described in more detail below, with reference to figure 8. The block diagram of an element EC switching switch "will be described in more detail below, with reference to Figure 12.

The MPSN network being of the multipath type, all the cells constituting the same block do not necessarily pass through the same switching element EC "in a given intermediate stage. On the other hand, all the cells of the same block will end up at the same output port PS recipient "with the exception of cells that have been lost or eliminated. It would therefore be difficult to seek to eliminate additional cells in the various switching elements EC "of an intermediate stage, capable of routing these cells, based on the fact that a cell belonging to the same block has already been lost by any of these EC switching elements "; this would require complex exchanges of messages between switching elements. On the other hand, the elimination of additional cells can be carried out efficiently in the output port PS "to which all cells belonging to the same block converge, if this output port is aware of the blocks disturbed by at least one cell loss in the 'any of the EC switching elements'
For this purpose, for each cell lost in an EC switching element ", this element generates a cell known as cell loss signaling cell, CSCP. The cell loss signaling cell is advantageously much smaller in size than the cells transporting data, because it only contains: a characteristic code for cell signaling cell loss, as well as the characteristic data associated with the lost cell: the block identifier, the identifier of the connection which transported the block from which a cell is lost, and the auto-routing label. This auto-routing label allows the cell loss signaling cell to be routed in the same way as a data cell. , up to the destination port (s) PS "of the MPSN network.

Each output port PS "performs the functions of the output port PS 'described with reference to FIG. 1, to eliminate all the cells, except possibly the last cell, belonging to a block for which this same output port has already lost a cell; and further it detects cell loss signaling cells,
CSCP, emitted upstream, by the switching elements EC ", and controls the elimination of all the cells according to the cell lost in the disturbed bioc, with the possible exception of the last.

 According to a first alternative embodiment of the SPSN and MPSN networks, the authorization to eliminate the last cell is given by an EDCA indicator called "last authorized packet elimination indicator" The input ports PE ', the elements EC'and EC "switching ports, the PS'and PS" output ports have an EDCA indicator locally for each connection, this indicator being marked when establishing the connections.

 According to a second alternative embodiment of the SPSN and MPSN networks, the authorization to eliminate the last cell is given by an IAEDC indicator called "last cell elimination authorization indicator", this indicator being associated by the port of input to each cell by placing it in a header, as well as the other characteristic data of the block to which the cell belongs.

Each switching element EC "must allow the transmission of a cell loss signaling cell, in spite of possible saturation of the buffer memory which was the recipient of the lost memory. A third and a fourth alternative embodiment are possible to allow this transmission:
-Either the cell loss signaling cell is stored in the buffer of this switching element to queue with other cells. In this case, it is necessary to always keep a certain buffer memory capacity in order to be able to store a cell loss signaling cell in each buffer memory.

 -Either the cell loss signaling cell is transmitted without delay, and therefore without being stored in the buffer of the switching element, but the service of this buffer must be interrupted, that is to say the reading of the data cells in the buffer memory, for a duration corresponding to the priority transmission of the signaling cell.

 In view of the low probability of cell loss, these two alternative embodiments of the switching element EC "modify little its characteristics and its traffic performance compared to a conventional element.

FIG. 3 represents, for reference, the block diagram of a PE input port of a conventional switching network. It includes:
a device STC for temporary cell storage, having an input connected to an incoming line LE, an output connected to switching elements (not shown) of the first stage of the switching network considered;
-a TECC device, called incoming cell layer termination, having an input connected to the incoming line LE for pre) ever! are the headers of the arriving cells, and having an output providing data which will be incorporated into so-called internal cells which are the cells to be switched in the switching network considered,
-and a PCI device for preparing internal cells, having an input connected to the output of the TECC device, and an output connected to an input of the STC device to supply it with data and control signals to prepare internal cells, these these being formed by adding routing data to cells arriving on the incoming line LE.

FIG. 4 represents the block diagram of an input port PE 'of an asynchronous switching network, with single-path routing, provided with the device according to the invention. Such an entry port includes:
-an STC 'temporary cell storage device, similar to the device
STC;
-an incoming cell layer termination, TECC ', analogous to the device
TECC;
PCI device for preparing internal cells, similar to the device
PCI;
an RBD device for recognizing data blocks, having an input connected to the incoming line LE for taking data from the adaptation layer between the cell layer and the data block layer, that is to say typically data used to define the segmentation of a data block into cells; and having an output providing IBD information on the data blocks, comprising in particular a so-called structure type indicator, determined at the time of establishment of a connection, this indicator indicating whether each cell of this connection is, or n ' is not, a subset of a block which has been divided into a series of cells, each cell possibly containing, for example, part of the data representing a video frame;
and an ADCB device for allocating block characteristic data, having an input connected to the output of the RBD device, and an output connected to a second input of the device PCI ′ to supply it with DCB characteristic data for each block received; the characteristic DCB data of a block being made up:
- a block identity, ITB, which is specific to the block to which the
cell, for the duration of its transport in the network, and which is asso
linked to all cells belonging to this block, this ITB block identity
being itself made up of a block identifier and an identifier
connection;
- a last cell indicator, IDC, indicating whether this cell is, or
is not, the last cell in a block;
- and, only for the second variant of embodiment mentioned before
ceded about Figure 2, an IAEDC authorization indicator
last cell disposal, which indicates authorization or inter
diction to eliminate the last cell.

FIG. 5 represents the block diagram of an output port PS of a conventional asynchronous switching network. It includes:
a cell multiplexer MC, having a plurality of inputs connected respectively to outputs of switching elements (not shown) of the last stage of the network, and having an output connected to an outgoing line LS;
-and a CMS device for controlling multiplexing of output, having inputs connected respectively in parallel to the inputs of the device MC, and having an output connected to a control input of the device MC to control the multiplexing of the cells supplied by the last stage d 'switching elements.

 The CMS control device interprets the headers of the cells supplied by the top stage, in order to develop the control signal making it possible to dynamically manage the multiplexing of the cells in the cell multiplexer MC. The latter includes a buffer memory to solve the contention problems, when several cells arrive simultaneously on the inputs of the multiplexer MC.

FIG. 6 represents the block diagram of an output port PS 'of an asynchronous switching network, with single-path routing, provided with a device according to the invention. This PS'output port includes:
a cell multiplexer MC ′, analogous to the multiplexer MC, having inputs connected respectively to outputs of the last stage of switching elements, and having an output r
- a second output providing a DTFS test request signal
selective filtering,
a third output providing a CMBP signal for controlling
memorization of a disturbed block,
- and a fourth output providing the characteristic DCB data
of a block;
a device GBP 'called disturbed block management device, having three inputs connected respectively to the second, to the third, and to the fourth output of the FSC device', and an ICE output providing to an input of the FSC device ', a cell indicator signal to be eliminated;
-and a CMS'of output multiplexing control device, similar to the CMS device, having an input connected to the FSC device for receiving the ICA signal indicating accepted cell signal, a first output connected to an input of the device
FSC 'to provide it with a signal ICP indicating a lost cell, and a second output connected to a control input of the cell multiplexer MC'.

The GBP'and FSC'collaborate for:
memorizing the identity of each block which is disturbed by the loss of at least one cell;
the detection of a cell belonging to a disturbed block;
-the selective elimination of cells belonging to a disturbed block;
and erasing the identity of each disturbed block memorized when this block identity is no longer used.

The device FSC 'for selective cell filtering provides the device GBP' with DCB data characteristic of a block, which are made up:
-a block identity, ITB, itself composed of a block identifier and a connection identifier (not distinguished in the figure);
a last cell indicator, IDC, indicating that the cell received is the last of a data block;
-and a local EDCA indicator for the elimination of the last authorized cell, for the first variant of the SPSN and MPSN networks; or an IAEDC indicator for authorization to eliminate the last cell, for the second variant.

FIG. 7 represents the block diagram of an exemplary embodiment of the device GBP ′ for managing disturbed blocks, specifically designed for the SPSN switching network with single-path routing. This example essentially includes:
-an input called DTFS receiving the DTFS signal for a selective filtering test request,
an input called CMBP receiving the disturbed block storage command CMBP signal,
an entry called ITB receiving the ITB identity of a block comprising an ITPB block identifier and a PBC connection identifier,
an entry called IDC receiving an IDC indicator of the last cell of the block concerned,
an input called EDCA receiving the EDCA signal indicating elimination of the last authorized cell, for the first variant embodiment,
- an ICE output providing the ICE signal indicating the cell to be eliminated,
a memory MIBP called memory of disturbed block identities, which is a memory of the memory type addressable by its content,
an MPBP memory called block parity memory, which is a memory of conventional type,
-and a GAL free address management circuit, which manages the free addresses of the MIBP memory.

 The function of this MIBP memory consists in memorizing the identities of disturbed blocks. It makes it possible to detect whether or not a received cell belongs to a disturbed block. While other solutions are possible, the choice of a memory addressable by its content is appropriate because the maximum number of objects (namely disturbed block identities) to be stored simultaneously is much smaller than the maximum number d 'possible objects. Indeed, the number of disturbed block identities is (normally) much smaller than the maximum number of possible block identities, ie all the possible values of the block identity code.

 To perform this function of memorizing disturbed block identities, a first solution consists in memorizing the block identity ITB defined above, which is supplied to GBD 'by FSC'. In order to ensure the erasure, in all cases, of a disturbed block identity which is no longer used, as will be explained below, another solution is used in the example of GBD device described here, namely the memory MIBD stores ITPB identities called "block pair identities" For this, the block identifiers are defined in pairs, called block pair identifiers, and the two block identifiers of a pair are characterized by a PB bit called "block parity"; thus, these two blocks have the same block pair identifier, but a different value of the bit PB. Since the identity of an ITB block consists of its ITPB block identifier and the PBC identifier of its connection, an ITPB block pair identity is thus defined by its block pair identifier and the identifier connection; then, a given block identity ITB corresponds to a block pair identity ITPB associated with the block parity bit PB of the particular block considered in the pair.

 In the example of a device GBP 'described here, the memory MIBD therefore stores block pair identities ITPB, and the block parity PB of the disturbed block considered is stored in a separate memory MPBP called disturbed block parity memory. This memory MPBP uses the same addresses as the memory MIBD, to associate a block parity PB with an identity of pair of blocks ITPB.

The GAL circuit for managing free addresses includes:
-A PALS output providing a first free address selected;
an input PA connected to the input CMBP to signal to the GAL circuit the acquisition of the address PALS;
- a NALS entry to provide it with a new free address,
-and an LA entry to signal the release of the NALS address.

Various embodiments are known for such a free address management circuit. A conventional embodiment, of the linked list type, comprises:
-a free address management memory, MGAL, having a data input connected to the NALS input, an ECR2 write command input connected to the input
LA, a read command input LECT2 connected to the input PA, a read / write address input, and a data output; the set of address values of this memory being chosen to be identical to the set of address values of the MIBP memory;
a multiplexer 11 with two inputs and one output, for transmitting either a read address or a write address to the memory address input
MGAL;
-a PDAL1 read address pointer, consisting of a register, having a data input connected to the NALS input, a write command input connected to the LA input, and an output connected to an input of the multiplexer 11;
-and a PDAL2 write address pointer, consisting of a register, having a data input connected to the data output of the MGAL memory, a write command input connected to the PA input, and a output connected to the other input of the multiplexer 11 and to the PALS output.

The disturbed block pair identity MIBP has:
-an ADR address entry,
a first and a second data entry corresponding respectively to two fields (ITPB, IV) for each address, a first being connected to the ITPB part of the ITB entry, and a second intended to receive a validity indicator IV consisting of 'a single bit;
-An entry ECR1 of write command for the two fields (ITPB, IV),
-a zero reset entry RAZIV for field IV;
an IDENT identification control input, to trigger the search for a word (ITPB, IV) possibly equal to the binary word applied to all of the two data inputs;
a RESID output providing a signal indicating whether the result of this search is positive or negative;
-and an ADRITB output providing the NALS input of the GAL circuit with the address at which the search has possibly found the word (ITPB, IV) sought.

 In this exemplary embodiment, all the values of the ITPB field are used, including the value zero. To identify the locations of the MIBP memory which contain non-significant values, a validity indicator IV is provided which is reset to 0 when it is meant to signify that the content of the ITPB field associated with this indicator IV is no longer significant. Thus, there is no need to initialize the ITPB field to a particular value (0 for example) in all of the MIBP memory when the device is started, and there is no need to reset a given location by y entering this particular value to signify that it no longer contains valid data.

In other exemplary embodiments, it would be possible not to use a value indicator, and to carry out a reset.

The disturbed block parity MPBP memory has:
-an ADR address entry ',
-a data input connected to the PBC part ("cell block parity") of the ITB input,
a PBM data output ("memorized block parity") connected to the block parity comparator CPB,
an ECR3 write command input connected to the CMBP input,
-and a read command input LECT3 connected to the RESID signal leaving the MIBP memory.

The GBP'possess in:
a multiplexer 6 with two inputs and one output, the latter being connected to the second data input of the MIBP memory;
an inverter 4 having an output connected to a first input of the multiplexer 6;
- an OR gate 5, having two inputs connected respectively to the inputs
DTFS and CMBP, and an output connected to a second input of the multiplexer 6;
-a multiplexer 7 with two inputs and one output, one input being connected to the ADRITB output of the MIBP memory, another input being connected to the PALS output of the GAL circuit, and the output being connected to the ADR address input MIBP memory,
a binary block parity comparator, CPB, having an input connected to the output PBM of the memory MPBP and another input connected to the PBC part of the input
ITB, and providing an MPB ("same block parity") signal of value 1 when the comparison is good;
an AND gate 3 having an input connected to the IDC input, an input connected to the RESID output of the MIBP memory, an input connected to the MPB signal leaving the comparator CPB, and an output connected to an input of the OR gate 12 ;
an inverter 9 having an input connected to the MPB signal leaving the comparator CPB,
an AND gate 10 having an input connected to the output of the inverter 9, an input receiving the RESID signal leaving the MIBP memory, and an output connected to an input of the OR gate 12;
an OR gate 12 having an input connected to the output of the gate ET10, an input connected to the output of the gate AND 3, and an output connected: to the input RAZIV of the MIBP memory, at the input of the inverter 4, and at the input LA of the GAL circuit;
an AND gate 2 having three inputs, one of which is connected to the RESID output of the memory MIBP, and another is connected to the MPB signal leaving the comparator CPB, and having an output connected to the ICE output;
an OR gate 1 having two inputs, one of which is connected to the EDCA input, and an output connected to the third input of the AND gate 2;
-and an inverter 8 having an input connected to the IDC input, and an output connected to the other input of the OR gate 1.

 The operation of the device GBP ′ comprises a phase for memorizing a disturbed block, and a phase for identifying a disturbed block.

Consider the case of memorizing a disturbed block. When a cell is lost in the output port, PS ', a CMBP = 1 signal is applied to the input
CMBP, and DCB data characteristic of the disturbed block are applied to the ITB, IDC, EDCA inputs. The CMBP signal controls the storage of the ITB identity of the disturbed block, namely ITPB in the MIPB memory and PBC in the memory
MPBP. This signal is applied to a write command input ECR1 of the memory MIBP, and to the first input of an OR gate 5. The output of the OR gate 5 therefore supplies a signal of value 1 to the second data input from memory
MIBP, via multiplexer 6. The ITPB identity of the block pair corresponding to the disturbed block is applied to the first data entry in the MIBP memory. The signal CMBP = 1 therefore commands the writing of the identity ITPB and of a validity indicator IV = 1 in the memory MIBP at a free address ALS1 which is provided by the output
PALS of the GAL circuit, via the multiplexer 7.

 The CMBP signal is also applied to the address input PA input, in the GAL circuit for managing free addresses. It thus controls the storage of the fact that the address ALS1, which is currently provided by the read address pointer PDAL2, is no longer free. For this, it is applied to the write command input of the read address pointer PDAL2 to update it by writing there a new free address ALS2 which is currently read in the memory MGAL at the address ALS1; and it is also applied to the read command input LECT2 of the memory MGAL in order then to read a next free address ALS3 which is stored at the address ALS2. The signal CMBP is also applied to the write command input ECP 3 of the memory MPBP to register the block parity PBC, received at input) ITB, at the same free address ALS1 supplied by the circuit GAL via the multiplexer 7 as ADR address'.

 Consider the case where the selective cell filtering device FSC emits a selective filtering request signal DTFS = 1 for a cell which has just been received, and provides data DCB = (ITB = ITPB + PBC, IDC, EDCA) corresponding to the cell received.

 Before describing the corresponding operation, it is necessary to explain the described solution which is based on the use of pairs of block identities, in order to ensure that the device GBP 'correctly releases a data block identity, memorized in all cases, each time the same identity is re-used for a new data block. Indeed, in the case of a solution simply based on the memorization of the identity of the disturbed block, itself, in the MIBP memory, and where the erasure of this identity would be carried out during the reception of the last cell of the corresponding block, there is a certain risk that this last cell is lost in an upstream switching stage, and therefore that the function GBP ′ cannot correctly erase its block identity when it is finished. Subsequently, when the same block identity is again used for a new block of this same connection, the function GBP ′ would still find this stored identity, would consider that this block is disturbed (upon receipt of its first cell), and would remove all cells from this block.

 The solution described is an example which makes it possible to overcome this drawback, by defining the block identities in pairs as explained above, and by establishing the rule that, in the input ports PE ′, when a free block pair identity is assigned to a new data block, the block identity is such that its block parity PB is different from that used the previous time for the same block pair identity (principle of alternating block parity, such as PB = 1 (or 0) is affected if PB = 0 (or 1) was used previously). The alternate assignment of the two block identities of each block pair identity then allows the GBP'device to further detect the reception of a (first) cell of a (new) data block whose pair identity of blocks is stored in MIBP, but whose PBM stored block parity is different from the PBC cell block parity. It is then the first cell of a new data block (using the same block pair identity), and the device GBP 'detects the fact that the identity of the previous block (using the same pair pair identity) blocks) has not been correctly erased; it must therefore erase it immediately from the MIBP memory.

The signal DTFS = 1 is transmitted by the OR gate 5 and the multiplexer 6 to the second data input of the MIBP memory. The ITPB block pair identity corresponding to) the received cell is applied to the first data entry of the MIBP memory. The signal DTFS = 1 being also applied to the IDENT input of the MIBD memory, it triggers an identification operation in this MIBP memory, to find a word identical to the word (ITPB, IV = 1) which is applied to the inputs data this memory. The MIBP memory provides the result of this search on its RESID and ADRITB outputs:
-The RESID output provides 1 or 0 depending on whether the search has found a word identical to the word sought or not (ITPB, IV = 1);
-The ADRITB output provides the address where the word was found (ITPB, IV = 1) if such a word was found.

The signal RESID = 1 then commands the reading of the MPBP memory (command reading LECT3) at the address identified ADRITB received on the address input
ADR'via the multi plexer 7. At the output of the memory MPBP, the stored block parity PBM is then supplied to the block parity comparator CPB which compares it with the block parity of the cell, PBC, received as part of the ITB input data:
-If the comparison result is positive, the comparator provides a signal
MPB ("same block parity") of value 1 indicating that the received cell belongs to a disturbed block;
-If the result of the comparison is negative (MPB = 0), the cell received is the first of a new block which must not be considered as disturbed, and the identity of pair of blocks ITPB identified in the memory M1PB must be immediately deleted.

 Let us first consider the case where the result of the comparison is positive, therefore MPB = 1. When such a word has been found (RESID = 1), if the cell is not the last in a block (IDC = 0) and if the signal MPB = 1, then the output of AND gate 2 provides a ICE signal = 1 indicating that the cell is to be eliminated. When such a word has been found (RESID = 1), if it is the last cell of the block considered (IDC = 1), if its elimination is authorized (EDCA = 1), and if the signal MPB = 1, then the output of the AND gate 2 likewise provides a signal (ICE = 1) indicating that the cell is to be eliminated; and the output of the AND gate 3 supplies to the OU12 gate a signal LBPDC = 1 called block release signal by a last cell.

Now consider the second case where the result of the comparison is negative (MPB = 0). In this case, the gate ET2 always provides a signal ICE = 0, indicating that the cell must not be eliminated, and the gate ET3 always provides a signal
LBPDC = 0, indicating that this is not a block release disturbed by the loss of the last cell.

On the other hand, after the MPB signal = 0 has been inverted by the inverter 9, the door
ET10, receiving the signal RESID = 1 and an active signal supplied by the output of the inverter 9, generates a block release signal disturbed by another parity, LBPAP = 1, applied to the other input of the gate OU12. The signal supplied by the output of gate 12, called disturbed block release, LPB, is applied to the write control input RAZIV of the memory MIBP. On the other hand, the LBP signal is inverted by the inverter 4 to apply a bit of value 0 to the second data input from the memory
MIBP. A validity indicator IV = 0 is thus associated with the identity ITPB corresponding to the block considered, to memorize the immediate release of this identity of pair of blocks.

Furthermore, the signal LBP = 1 is applied to the input LA of the GAL circuit for managing the free addresses. It is applied to the write command input of the write address pointer PDAL1, and to the write command input ECR2 of the memory MGAL. Simultaneously, the address ADRITB where the word was found (ITPB, IV = 1) is applied to the NALS input of the GAL circuit for managing free addresses. It is thus applied to the data input of the write address pointer PDAL1, and to the data input of the memory MGAL. The signal LBP = 1 therefore controls the writing of the address ADRITB in this memory MGAL to the address currently supplied by the writing pointer PDAL1, via the multiplexer 11. At the same time, the signal LBP = 1 controls the setting PDAL1 pointer, by writing the address ADRITB, just after the end of this write operation in the MGAL memory, so that
ADRITB is the next address provided by the PDAL1 pointer.

 FIG. 8 represents the block diagram of an output port PS "of an asynchronous switching network, with multi-route routing, provided with a device according to the invention. This output port PS" comprises almost the same means as the PS port 'previously described for a single-route routing network. These means respectively bear the same references but with the attribute ". The device FSC 'for selective filtering of cells is replaced by an FSC device" which is slightly different, since it comprises in addition to the means described above for FSC', means for detecting the reception of a CSPC cell loss signaling cell, and in this case asking the GBP device "to memorize (if it is not already done) the identity of the block signaled in the CSPC cell as a disrupted block identity.

The GPB 'device for managing disturbed blocks is replaced by a device
GPB "which is slightly different because it includes, in addition to the means described above for GBP ', time delay means for making a disturbed block identity available, after the reception of the last cell in this block, with a delay at least equal to the maximum value of the transfer time of a cell through the network.

FIG. 9 represents the block diagram of an exemplary embodiment of the device “GBP for managing disturbed blocks, specifically designed for a switching network with multi-route routing. This example comprises, in addition to the means described above for the device GBP ', an FTG timer which is inserted on the ADRITB output of the MIBP memory and on the output of the AND gate 3. This FTG timer includes:
-an input linked to the ADRITB output to receive an address to be delayed,
an input connected to the output of the AND gate 3 to receive a DTG signal for triggering the time delay,
-an output providing an ADRITB 'delayed address,
and an output supplying the OR gate 6 with the signal LBPTG which then consists of the signal DTG delayed by the same delay as the address ADRITB.

As in the GBP 'device, the GBP "device can perform two types of disturbed block release, depending on the result of the block parity comparison (at the output of the CPB comparator), MPB = 1 or 0:
-If MPB = 1, it is a release caused by the reception of the last cell of the disturbed block stored, in which case the release is delayed by the FTG guard timer function as described above.

 -If MPB = 0, this is a release caused by the first cell of a new data block, using an identity of pair of ITPB blocks still stored (for the previous block using the other block parity ), in which case the release of the ITPB still stored must be immediate; for this the block release signal disturbed by another parity (LBPAP = 1), generated by gate 10, is supplied directly to gate OU12 (which generates the disturbed block release signal = 1), without going through the FTG timer function.

It should be noted that the exemplary embodiment of a GBP device "based, like GBP ', on the definition of block identifiers in pairs and on the principle of alternate assignment of the two block identifiers (of each pair of block identifiers ) to the new data blocks by the input ports PE ', has the advantage of ensuring the correct release of identities, of disturbed block, also in another case than that where the last cell of a disturbed block would be lost upstream of the addressee PE outlet port (s). Indeed, in the case of a multi-path switching network MPSN and if the latter is capable of delivering the cells to the output ports PS "in an order different from the order of arrival of the cells at the input ports PE ' , it is possible that, among the cells of a block, received after the last cell of this block, one of them is lost and thus causes the storage in PS of the identity of the corresponding block as a disturbed block. Since this storage is carried out after the reception of the last cell, the identity of pair of ITPB blocks stored in the memory MIBP of the device GBP "cannot, in this case, be released by the reception of the last cell; it can only be released later by receiving the first cell received for a new block using the same ITPB block pair identity and the other block parity
PB, in accordance with the solution used in the GBP device exemption "to ensure the correct release of disrupted block identities in all cases.

 A small difference will also be noted for the address signal ADR 'of the memory MPBP, which is supplied, in the device GBP ", by a multiplexer 13 having an input connected to the output ADRITB of the memory MIBP and another input connected to the output of the multiplexer 7.

PS output ports "detect CSPC cell loss signaling cells, which are emitted by the switching elements upon cell loss. Each CSPC cell loss signaling cell has the same routing data (usually a label auto-routing) than the lost cell, in order to be able to be routed to the destination port (s) of output (s) in the same way as the lost cell. It is therefore detectable at each port of output which is a destination of the block considered, whatever the various possible paths for transferring the cells of this block. It also contains the same connection identifier, as well as the lost cell identifier. To process the CSPC cells, the FSC device "which is associated with each PS output port" further comprises:
means for detecting the reception of a CSPC cell loss signaling cell;
-and means to register, in <R
an FSC 'device for selective filtering of cells, analogous to the FSC device described above for the PS'output ports and having:
- inputs connected respectively in parallel with the inputs of the
matrix Ml ';
- a first output providing an ICA indicator of accepted cell;
- a second output providing a memory storage command
disturbed block, CMBP;
- a third output providing a request for a dry filter test
lecturer, DTFS;
- and a fourth output providing data characteristic of a
block, DCB;
a device GBP ′ for managing disturbed blocks, analogous to the device GPB described above, and having a first, a second and a third input connected respectively to the second, third and fourth output of the FSC device, and having an output connected to an input of the FSC 'device to provide it with an indicator
Cell ICE to be eliminated;
a cell routing control device CAC ', having an input connected to the first output of the device FSC', a first output connected to an input of the device FSC 'to provide it with a lost cell indicator ICP, and a second output connected to a control input of the interconnection matrix Ml 'to provide it with a control signal.

 According to this embodiment, the management of the disturbed blocks is similar to that carried out for the output port PS 'described previously with reference to FIGS. 6 and 7, the device GBP' also comprising a MIBP memory, for example of the memory type addressable by its content, an MPBP memory, and a GAL circuit.

Figure 12 shows the block diagram of a switching element
EC "of an asynchronous switching network provided with a device according to the invention, according to a second embodiment specifically designed for a multi-path switching network. This second embodiment allows each switching element to transmit a cell so-called cell loss signaling, CSPC, when a cell is lost in this switching element. The emission of a CSPC cell is only necessary if the DCB data which is associated with this lost cell indicates that it belongs to a data block.

 This second embodiment is particularly designed for multi-path asynchronous switching networks. However, it can also be used in single-route networks.

The switching element EC "shown in FIG. 12:
an interconnection matrix MI "having inputs connected respectively to outputs of switching elements of a preceding stage or to outputs of input port; and having a plurality of outputs connected respectively to inputs of elements switching to a next stage or to output ports;
-a CAC device "cell routing control, having inputs connected respectively in parallel with the inputs of the matrix MI", a first output providing a cell loss indicator IPC, a second output providing DCB data characteristic of 'a block, and a third output providing a control signal to a control input of the matrix MI ";
-and a GCSPC device for generating cell loss signaling cells, this device comprising a first and a second input connected respectively to the first and to the second output of the CAC device ", and having an output connected to an additional input of the matrix Ml "to provide it with a cell
CSPC signaling cell loss, in order to transmit it downstream.

As mentioned above, the FSC device "which is associated with each PS output port", represented in FIG. 8, further comprises, for processing the CSPC cells:
means for detecting the reception of a cell;
and means for recording, in the memory MIBP of the device GBP "associated with this device FSC", the identity of the disturbed block, also during the reception of a CSPC cell.

 According to a preferred embodiment, the CSPC cells have a smaller size than the cells transporting data, which facilitates their transfer to the exit port (s) concerned in the event of traffic overload.

 According to a preferred embodiment, for a multi-path switching network in which all the cells belonging to the same block do not necessarily follow the same path, and in which the output ports PS "do not necessarily receive the cells of a block in the order in which they were received by the input ports PE ', the devices GBP "for managing disturbed blocks in the output ports PS" include a guard timer at the output TGS to erase an identity of disturbed block, in the MIBP memory of disturbed block identities, after) the reception of the last cell of this block, with a minimum delay at least equal to the maximum variation of the transfer time VMTT of a cell across the network .

 On the other hand, the ADCB devices for allocating block characteristic data in the input ports PE ′ furthermore include a guard timer at the input TGE to make a block identity available after the transmission of the last cell of this block, with a minimum delay at least equal to twice the maximum variation of the transfer time VMTT of a cell through the network. In fact, in an output port PS ", the maximum delay between the reception of the penultimate cell of a data block and the reception of the last cell of this block, when these two cells are not received in the correct order, is at most equal to the maximum variation of the transfer time VMTT of a cell in the network.

By applying a guard delay at least equal to VMTT upon receipt of the last cell before releasing the disturbed block identity, an output port PS "is therefore certain to have received all the cells of the block in question.

 Knowing that the output ports PS "introduce a guard delay at the output TGS greater than or equal to VMTT, the input ports PE ′ must take this into account by not reusing a block identity before a guard delay at the TGE input greater than or equal to TGS + VMTT, this time delay being consecutive to the emission of the last cell of the block having used this same identity, in order to take into account both the maximum transfer time VMTT of the last cell, and the guard delay at the output TGS (greater than or equal to VMTT) introduced by the output ports PS "after the reception of this last cell.

 The introduction of guard timers in PE 'and in PS "avoids numerous signaling exchanges between the output ports and the input ports which would be necessary to synchronize the release of the data block identities.

FIG. 13 represents the flow chart of the operations carried out in the switching elements EC ′ and in the output ports PS ′ of the SPSN network with single-path routing, during the transfer of a cell. The operations carried out by:
-an SMD device for controlling output multiplexing, or a device
CAC 'for cell routing control, depending on whether the cell is being processed in an output port PS' or in a switching element EC ';
a device FSC ′ for selective filtering of cells, when the cell is being processed in an output port PS ′ or in a switching element EC ′;
a device GBP ′ for managing disturbed blocks, when the cell is being processed in an output port PS ′ or in a switching element
EC '.

 An operation 1 consists in receiving a new cell and in taking the additional header which contains the characteristic DCB data of the block to which this cell belongs, if applicable. These characteristic data are: the block identity, ITB (consisting of a block identifier and a connection identity), and the last cell indicator, IDC (the example considered corresponds to the first variant embodiment , therefore the DCB data transported by the additional header does not include the indicator IAEDC). The block identity makes it possible to completely identify the block to which the cell in question belongs, whatever the protocol for adapting the blocks to the asynchronous transfer mode. The FSC device provides the GBP device with DCB data, including the local indicator EDCA "Elimination of last authorized cell" which is marked in this FSC device when establishing the connection considered (in accordance with the first variant).

On the other hand, the device FSC'provides to the device GBP'the signal DTFS "request for selective filtering test.

An operation 31, performed by the device GBP ', compares the identity of block pair ITPB with other identities of pair of blocks, stored in the memory
MIBP of the GBP function, and designating block pairs of which one of the blocks is, or has been disturbed, i.e. in which at least one cell has been lost:
-If operation 31 does not find the same ITPB block pair identity in
MIBP, the cell can be processed normally, and the device GBP'transmits to the device FSC'an signal ICE = 0 indicating that the cell must not be eliminated.

-If operation 31 finds the same ITPB block pair identity in MIBP, operation 32 determines whether it is the identity of the block to which the cell belongs or the identity of a previous block which has not been released, depending on whether the block parity of the PBC cell is identical or different with respect to the stored block parity PBM read in the MPBP memory:
--If the PBC block parities are different (MPB = 0), the available
sitive GBP 'concludes that the cell should not be eliminated and provides the dis
positive FSC 'an ICE signal = 0; on the other hand, he commands, by operation 33,
releasing the ITPB block pair identity identified in MIBP.

--If the PBC and PBM block parities are identical (MBP = 1), the
GBP device concludes that the cell belongs to a disturbed block, and it realizes
read an operation 3 which tests the value of the last cell indicator,
IDC:
--- If this IDC flag indicates that it is not the last
cell of a block, the device GBP'provides to the device FSC'a signal
ICE = 1 indicating that the cell is to be eliminated. The process ends
mine in state 6 where this cell is eliminated: either the FSC'ne device
did not write it in the buffer, or deleted it if each
cell is systematically registered without waiting for the result
tests 31, 32 and 3.

--- Conversely, if the IDC last cell indicator indicates
that it is the last cell of a block, the GBP device is erased
ITPB identity immediately in MIBP memory (which is rea
list in this example, by zeroing the validity indicator IV which
is associated with ITPB in this memory). Then the GBP'test device,
by operation 5, the last cell elimination indicator at
toisée, EDCA. If disposal is permitted, GBP'provides
an ICE = 1 signal to the FSC device which eliminates the cell, and the pro
cessus ends with the state referenced 6. In the event that elimination
of the cell is not authorized, the GBP device supplies to the device
FSC 'the signal ICE = 0 indicating that the cell is not eliminated.

When the FSC device receives an ICE = 0 signal from the GBP device, it normally processes the cell. 11 then provides the device CMS ', respectively CAC', the signal ICA = 1 indicating that the cell is accepted. The CMS 'device, respectively
CAC ', then routes the cell normally. During this routing, it can happen that this cell is lost (either because of the saturation of the recipient buffer memory of the cell, or because of a fault affecting the cell).

To take account of this eventuality, an operation 7 is carried out in the device CMS ', respectively CAC', to characterize the possible loss of the cell treated. For this, the device CAC 'in a switching element EC', respectively CMS 'in an output port PS', checks whether the cell is not lost:
-If the routing goes wrong (cell not lost), the normal process
ends at the step referenced 8.

-If the cell is lost for any reason, an indicator of
lost cell, ICP = 1, is supplied to the FSC 'device. The FSC'teste system
then, by an operation 9, the value of the IDC indicator of the last cell:
--If the IDC indicator indicates that it is not the last cell of a
block, it is necessary to memorize in the memories MIBP and MPBP
the identity of the block to recognize other cells of this block which ar
will flow later. The FSC device provides the GBP device
the storage command signal CMBP = 1, and the data
DCB characteristics of the disturbed block. The GBP device makes a
operation 10 which consists in memorizing the identity of pair of blocks
ITPB in MIBP memory and PBC cell block parity
in MPBP memory. Then the process stops at the reference stage
11.

--If the IDC indicator indicates that it is the last cell, it is useless
to memorize the block identifier since no cell appears
nant to this block will not appear later, therefore the
process ends at the step referenced 11, without additional operation.

 According to an alternative embodiment, the ADCB devices do not generate an IAEC elimination authorization indicator, and the test operation 5 is deleted. The last cell is systematically eliminated after operation 4. This variant can only be used for adaptation protocols which do not depend critically on the reception of the last cell to determine the end of each block.

 According to another variant, whatever the data block adaptation protocol used, the last cell is never eliminated. Operation 4 is then followed directly by test operation 7 consisting in determining whether this latter cell has been routed normally or whether it has been lost; in other words test 5 is deleted as well as the indicator for elimination of last authorized cell EDCA. This variant makes it possible to simplify the management of data loss while systematically preserving the last cell of each block for the services which need it to delimit the blocks.

 The switching network releasing SPSN being of the single-path type, the order of the cells of a block is preserved. It is certain that no other cell of the block considered will be received after the cell carrying the last cell indicator. The device ADCB for assigning the characteristics of the data block, of the input port PE ′, also noting the end of the block considered, can immediately reuse this identity of pair of blocks for a new block.

FIG. 14 represents a flow chart of the operations carried out in the output ports PS "of the MPSN network with multi-route routing, during the transfer of a cell. The operations carried out respectively are distributed by:
-a CMS device "for output multiplexing control.

-an FSC "selective cell filtering device,
- a GBP "device for managing disturbed blocks.

 Apart from the exceptions mentioned below, all the operations and steps are the same as those described above for the SPSN network. They then bear the same references and will not be described again. When a PS "output port receives a normal cell, operations 1,31,32,33,3 are unchanged. On the other hand, operation 4 (erasure of the identity of the disturbed block) is replaced by an operation 14 consisting, for the device "GBP", of launching a guard timer which delays the erasure of the identity of pair of blocks in the memory MIPB, in the case where the asynchronous switching network multi-path MPSN is likely to cause an imbalance of the cells of this block, such as the last cell would be received at the output port PS "before the arrival of one or more cells which normally precede it. This precaution also eliminates the cells belonging to the block considered which would arrive after the last cell in the block.

 The detection 12 of a CSPC cell for signaling cell loss by the FSC device "is followed by operation 31 (search for the ITBP identity in the MIBP memory) and subsequent ones in the GBP device" as for a normal cell.

Although this is not strictly necessary, it is advantageous in this case to make the FSC device "force the last authorized cell elimination indicator EDCA to 1 in the DCB data, relating to the lost cell, supplied to the GBP device ", regardless of the value of the EDCA indicator marked in the FSC device" for the connection considered. Indeed, the value of the ICE signal (cell indicator to be eliminated) supplied by the FSC device " then clearly characterizes whether the lost cell belongs to a disturbed block stored in the GBP device or not "
-If the lost cell belongs to a stored disturbed block, the result of test 32 is positive, and the signal ICE = 1 is then provided in all cases;
-If the lost cell does not belong to a disturbed block, the result of test 32 is negative, and the signal ICE = 0 is then provided in all cases.

The FSC device "performs an operation 13 additional to the previous case. This operation 13 determines whether the cell is a normal cell or a CSPC cell for signaling cell loss. In the case of a normal cell, this operation 13 leads then to do the operation 7 described above, in the case of a CSPC cell, it also leads to doing the operation 9 consisting in checking the indicator for the last cell IDC:
-If the cell signaled as lost is not the last cell in a block, the identity of the block is memorized by operation 10: the FSC device "supplies the device GBP": the DCB data characteristic of the disturbed block, and the block storage control signal CMBP.

 -If it is the last cell of a block, the process ends in state 11 because there is nothing more to do.

 This flowchart further comprises an operation 21 noting the expiration of the guard time delay before releasing the identity of the pair of blocks, and triggering an operation 22 which consists in erasing in the memory MIBP of the device GBP "the identity of pair of blocks of the disturbed block considered.

Claims (10)

 1) Device for managing data loss in a switching network  asynchronous data packets, with asynchronous transfer mode; each  packet which can be a subset of a data bioc transmitted on a con  nexion; each block being divided into a series of packets according to a protocol  adaptation of data blocks to asynchronous packet transfer mode, cha  that connection can use a different adaptation protocol; and this network  having input ports and output ports interconnected by at least one switching element, for transferring each packet from an input port to at least one output port, the output ports and the switching elements being capable of to lose a package;  characterized in that it:  -first means (RBD, ADCB) located at the entry ports (PE ') for  identify, for each connection, each packet belonging to a block and as  associate with this package:  --a structure indicator (IBD) indicating that this package is a sub  set of a block cut into a series of blocks,  --and a block identifier, internal, independent of the adap protocol  external station used for the connection carrying the block in question;  - second means (GBP ', FSC'; GBP ", FSC") located at least at  output ports (PS '; PS ") for:  - memorize a so-called disturbed block identity (ITB), for each block  which is disturbed by the loss, at least in these exit ports, of  minus one packet belonging to this block; this identity:  --- the identifier of this block,  --- and a connection identifier identifying the connection which  routes this block;  - detect, among the packets received by these second means, each  package whose structure flag indicates that this package belongs to  a block, and whose block identifier and connection identifier  correspond to a disturbed block identity (ITB) which is stored;  --and eliminate at least some of the packets thus detected.  2) Device according to claim 1, for a network (SPSN) in which all the packets belonging to the same block follow the same path, characterized in that the switching elements (EC ') liable to lose a packet comprise third means (GBP ', FSC') having functions similar to those of the second means (GBP ', FSC').  3) Device according to claim 1, characterized in that the switching elements (EC ") likely to lose a packet include means (GCSPC) for transmitting a packet (CSPC) said packet loss signaling, when a packet is lost in this element, at least when the structure indicator which is associated with this lost packet indicates that it belongs to a data block; this signaling packet being routed to the destination output port (s) to using the same routing data as that carrying the lost packet, and this signaling packet containing the identifier of this connection as well as the block identifier of the lost packet;  and in that said second means (GBP ", FSC") in the output ports (PS ") further comprise:  means (FSC ") for detecting the reception of a signaling packet  packet loss,  -and means (GBP ") to memorize the identity of a disturbed block, equal  when a packet loss signaling packet is received.  4) Device according to claim 3, characterized in that the means (GCSPC) for transmitting a packet loss signaling packet transmit a packet of size smaller than that of the lost packet.  5) Device according to one of claims 3 or 4, for a network (MPSN) in which all the packets belonging to the same block do not necessarily follow the same path, and in which the output ports (PS ") do not receive not necessarily packets in a block in the order they were received by the input ports;  characterized in that the second means in the output ports (PS ") furthermore comprises timer means for erasing a disturbed block identity, in the means for memorizing disturbed block identities, after reception of the last packet of this block, with a minimum delay at least equal to the maximum variation of the time for transferring a packet across the network;  and in that the first means (RBD, ADCB) in the input ports (PE ') furthermore include time-delay means for making available a disturbed block identity after the transmission of the last packet of this block, with a minimum delay at least equal to the sum of the maximum variation of the time for transferring a packet through the network and the delay time introduced in the output ports (PS ").  6) Device according to one of claims 1 to 3, characterized in that the second means (GBP ', FSC'; GBP ", FSC") and the third means (GBP ', FSC') if there are any , discard all the packets thus detected.  7) Device according to one of claims 1 to 3, characterized in that the first means (RBD, ADCB) of the input ports (PE ') comprise means for further associating, with each packet belonging to a block, a last packet indicator (IDC), indicating whether or not this packet is the last packet of the block to which it belongs;  and in that the second means (GBP ', FSC'; GBP ", FSC") in the output ports (PS '; PS "), and the third means (GBP', FSC '), if any a in the switching elements (EC '), include means for eliminating each packet which is detected as belonging to a disturbed block, if the indicator for last packet indicates that it is not the last packet for a block.  8) Device according to one of claims 1 to 3, characterized in that the first means (RBD, ADCB) of the input ports (PE ') comprise means for further associating, with each packet belonging to a block:  -a last packet indicator (IDC), indicating whether this packet is or  is not the last packet in the block to which it belongs;  -and an indicator (IAEDC) for authorization to eliminate the last pa  quet, indicating whether the elimination of the last packet from the block to which it belongs  is or is not authorized, this indicator being marked in the ports  input when establishing connections;  and in that the second means (GBP ', FSC'; GBP ", FSC") and the third means (GBP ', FSC') if there are any, include means for eliminating each packet which is detected as belonging to a disturbed block, unless the indicator (IDC) of last packet indicates that it is the last packet of a block, and if the indicator (IAEDC) of authorization to delete the last packet indicates that its elimination is not authorized.  9) Device according to one of claims 1 to 3, characterized in that the first means (RBD, ADCB) comprising means for further associating with each packet belonging to a block, an indicator (IDC) indicating whether this packet is or is not the last package in the block to which it belongs,  in that the first means (RBD, ADCB), the second means (GBP ', FSC'; GBP ", FSC"), and the third means (GBP ', FSC'), if there are any, locally available for each connection of an indicator (EDCA) called local indicator of elimination of last authorized packet, this indicator being marked during the establishment of the connections;  and in that the second means (GBP ', FSC'; GBP ", FSC") and the third means (GBP ', FSC'), if there are any, comprising means for eliminating each packet which is detected as belonging to a disturbed block, except if the indicator (IDC) of last packet indicates that it is the last packet of a block, and if the local indicator (EDCA) of elimination of last packet authorized indicates that its elimination is not allowed.  10) Device according to one of claims 1 to 3, characterized in that the block identifiers are organized in pairs, each block identifier being defined by a block pair identifier and a block parity in this pair of blocks;  in that the first means (RBD, ADCB) located at the input ports (PE '), for assigning a free block identifier to a new data block, select a free block pair identifier and a different block parity that used previously for this same block identifier;  and in that the second means (GBP ', FSC', GBP ", FSC") in the output ports, and the third means (GBP ', FSC') if there are any in the switching elements, release immediately the corresponding block pair identity if this is stored in said means and if the stored block parity, associated with the identified block pair identity in memory, is different from the cell block parity received.