FR2772946B1 - Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes - Google Patents

Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes

Info

Publication number
FR2772946B1
FR2772946B1 FR9716360A FR9716360A FR2772946B1 FR 2772946 B1 FR2772946 B1 FR 2772946B1 FR 9716360 A FR9716360 A FR 9716360A FR 9716360 A FR9716360 A FR 9716360A FR 2772946 B1 FR2772946 B1 FR 2772946B1
Authority
FR
France
Prior art keywords
operands
exception
format
determining
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9716360A
Other languages
English (en)
Other versions
FR2772946A1 (fr
Inventor
Claire Bonnet
Sebastien Ferroussat
Didier Fuin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9716360A priority Critical patent/FR2772946B1/fr
Priority to US09/206,000 priority patent/US6321248B1/en
Publication of FR2772946A1 publication Critical patent/FR2772946A1/fr
Application granted granted Critical
Publication of FR2772946B1 publication Critical patent/FR2772946B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
FR9716360A 1997-12-23 1997-12-23 Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes Expired - Fee Related FR2772946B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9716360A FR2772946B1 (fr) 1997-12-23 1997-12-23 Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes
US09/206,000 US6321248B1 (en) 1997-12-23 1998-12-04 Process for determining an overflow to the format of the result of an arithmetic operation carried out on two operands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9716360A FR2772946B1 (fr) 1997-12-23 1997-12-23 Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes

Publications (2)

Publication Number Publication Date
FR2772946A1 FR2772946A1 (fr) 1999-06-25
FR2772946B1 true FR2772946B1 (fr) 2004-01-30

Family

ID=9515002

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9716360A Expired - Fee Related FR2772946B1 (fr) 1997-12-23 1997-12-23 Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes

Country Status (2)

Country Link
US (1) US6321248B1 (fr)
FR (1) FR2772946B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535900B1 (en) * 1998-09-07 2003-03-18 Dsp Group Ltd. Accumulation saturation by means of feedback
US7206800B1 (en) * 2000-08-30 2007-04-17 Micron Technology, Inc. Overflow detection and clamping with parallel operand processing for fixed-point multipliers
US20040167954A1 (en) * 2003-02-21 2004-08-26 Infineon Technologies North America Corp. Overflow detection system for multiplication
US8209366B2 (en) * 2005-02-28 2012-06-26 Hitachi Global Storage Technologies Netherlands B.V. Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations
US7734114B1 (en) * 2005-12-07 2010-06-08 Marvell International Ltd. Intelligent saturation of video data

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH087670B2 (ja) * 1989-07-28 1996-01-29 日本電気アイシーマイコンシステム株式会社 加算回路
US5198993A (en) * 1989-12-04 1993-03-30 Matsushita Electric Industrial Co., Ltd. Arithmetic device having a plurality of partitioned adders
US5204832A (en) * 1990-03-22 1993-04-20 Matsushita Electric Industrial Co., Ltd. Addition apparatus having round-off function
DE4125120A1 (de) * 1991-07-30 1993-02-04 Standard Elektrik Lorenz Ag Binaerer akkumulator mit ueberlaufschutz
JP2789577B2 (ja) * 1995-02-07 1998-08-20 日本電気株式会社 加算オーバフロ検出回路
EP0780759A1 (fr) * 1995-12-22 1997-06-25 Lucent Technologies Inc. Elimination de retard de génération du drapeau de débordement mathématique dans un UAL
KR100236533B1 (ko) * 1997-01-16 2000-01-15 윤종용 배럴 쉬프터와 산술논리 연산기가 연결되어 있는 디지탈 신호 처리기 및 그 오버플로 검출방법
US5889689A (en) * 1997-09-08 1999-03-30 Lucent Technologies Inc. Hierarchical carry-select, three-input saturation
US6161119A (en) * 1998-11-05 2000-12-12 Microsoft Corporation Hardware multiplication of scaled integers

Also Published As

Publication number Publication date
FR2772946A1 (fr) 1999-06-25
US6321248B1 (en) 2001-11-20

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ST Notification of lapse

Effective date: 20070831