FR2752466B1 - Dispositif processeur integre de signaux numeriques - Google Patents

Dispositif processeur integre de signaux numeriques

Info

Publication number
FR2752466B1
FR2752466B1 FR9710434A FR9710434A FR2752466B1 FR 2752466 B1 FR2752466 B1 FR 2752466B1 FR 9710434 A FR9710434 A FR 9710434A FR 9710434 A FR9710434 A FR 9710434A FR 2752466 B1 FR2752466 B1 FR 2752466B1
Authority
FR
France
Prior art keywords
digital signals
processor device
integrated processor
integrated
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9710434A
Other languages
English (en)
Other versions
FR2752466A1 (fr
Inventor
Trong Nguyen Le
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2752466A1 publication Critical patent/FR2752466A1/fr
Application granted granted Critical
Publication of FR2752466B1 publication Critical patent/FR2752466B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
FR9710434A 1996-08-19 1997-08-18 Dispositif processeur integre de signaux numeriques Expired - Lifetime FR2752466B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US69710296A 1996-08-19 1996-08-19

Publications (2)

Publication Number Publication Date
FR2752466A1 FR2752466A1 (fr) 1998-02-20
FR2752466B1 true FR2752466B1 (fr) 2005-01-07

Family

ID=24799807

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9710434A Expired - Lifetime FR2752466B1 (fr) 1996-08-19 1997-08-18 Dispositif processeur integre de signaux numeriques

Country Status (7)

Country Link
US (1) US6425054B1 (fr)
JP (1) JP3954163B2 (fr)
KR (1) KR100280285B1 (fr)
CN (1) CN1129078C (fr)
DE (1) DE19735981B4 (fr)
FR (1) FR2752466B1 (fr)
TW (1) TW346573B (fr)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804726B1 (en) * 1996-05-22 2004-10-12 Geovector Corporation Method and apparatus for controlling electrical devices in response to sensed conditions
US5933855A (en) 1997-03-21 1999-08-03 Rubinstein; Richard Shared, reconfigurable memory architectures for digital signal processing
US6895452B1 (en) 1997-06-04 2005-05-17 Marger Johnson & Mccollom, P.C. Tightly coupled and scalable memory and execution unit architecture
WO1999060480A1 (fr) * 1998-05-15 1999-11-25 Richard Rubinstein Sous-systeme d'execution a antememoire reconfigurable et partagee
US7558472B2 (en) 2000-08-22 2009-07-07 Tivo Inc. Multimedia signal processing system
US6233389B1 (en) 1998-07-30 2001-05-15 Tivo, Inc. Multimedia time warping system
US6630945B1 (en) 1998-11-09 2003-10-07 Broadcom Corporation Graphics display system with graphics window control mechanism
EP1059781B1 (fr) 1999-05-06 2007-09-05 Siemens Aktiengesellschaft Dispositif de communication comportant des moyens de traitement en temps reel des données à transmettre
US6668299B1 (en) 1999-09-08 2003-12-23 Mellanox Technologies Ltd. Software interface between a parallel bus and a packet network
US6580767B1 (en) * 1999-10-22 2003-06-17 Motorola, Inc. Cache and caching method for conventional decoders
US6624819B1 (en) * 2000-05-01 2003-09-23 Broadcom Corporation Method and system for providing a flexible and efficient processor for use in a graphics processing system
DE10029675A1 (de) * 2000-06-23 2002-01-31 Dialog 4 System Engineering Gm Elektronisches Audiogerät
US7003450B2 (en) * 2000-10-20 2006-02-21 Pts Corporation Methods and apparatus for efficient vocoder implementations
KR100771728B1 (ko) * 2000-12-09 2007-10-30 엘지엔시스(주) 자동은행거래단말기에서의 상호 스레드 통신방법
US20030088407A1 (en) * 2001-04-02 2003-05-08 Yi Hu Codec
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
DE10254255A1 (de) * 2002-11-20 2004-06-17 Werner Wirsum Verfahren zur Leistungsbesserung von Audioanwendungen auf Computern unter Einbeziehung sog. Grafikkarten in die Datenberechnung
JP4542308B2 (ja) * 2002-12-16 2010-09-15 株式会社ソニー・コンピュータエンタテインメント 信号処理用デバイス及び情報処理機器
US20040128485A1 (en) * 2002-12-27 2004-07-01 Nelson Scott R. Method for fusing instructions in a vector processor
KR100463205B1 (ko) * 2003-02-13 2004-12-23 삼성전자주식회사 시퀀셜 버퍼를 내장하여 디에스피의 데이터 억세스 성능을향상시키는 컴퓨터 시스템 및 그 컴퓨터 시스템의 데이터억세스 방법
JP2007503787A (ja) 2003-05-19 2007-02-22 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ メモリ帯域幅要求が低いビデオ処理装置
JP2005057738A (ja) * 2003-07-18 2005-03-03 Canon Inc 信号処理装置、信号処理方法及びプログラム
JP4699685B2 (ja) * 2003-08-21 2011-06-15 パナソニック株式会社 信号処理装置及びそれを用いた電子機器
US7627039B2 (en) * 2003-09-05 2009-12-01 Realnetworks, Inc. Parallel video decoding
US6993598B2 (en) * 2003-10-09 2006-01-31 International Business Machines Corporation Method and apparatus for efficient sharing of DMA resource
WO2005050454A1 (fr) * 2003-11-18 2005-06-02 Matsushita Electric Industrial Co., Ltd. Memoire cache et procede de commande de celle-ci
US7136943B2 (en) * 2004-03-18 2006-11-14 International Business Machines Corporation Method and apparatus for managing context switches using a context switch history table
WO2005103922A2 (fr) * 2004-03-26 2005-11-03 Atmel Corporation Systeme sur puce a processeur de signaux numeriques a virgule flottante comprenant un domaine complexe a processeur double
ITMI20040600A1 (it) * 2004-03-26 2004-06-26 Atmel Corp Sistema dsp su chip a doppio processore a virgola mobile nel dominio complesso
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
KR100882949B1 (ko) 2006-08-17 2009-02-10 한국전자통신연구원 화소 유사성에 따라 적응적인 이산 코사인 변환 계수스캐닝을 이용한 부호화/복호화 장치 및 그 방법
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US20100191913A1 (en) * 2009-01-26 2010-07-29 Agere Systems Inc. Reconfiguration of embedded memory having a multi-level cache
CN101567732B (zh) * 2009-06-05 2012-07-04 北京派瑞根科技开发有限公司 实现模拟多媒体广播内容过滤的方法
EP2333673B1 (fr) * 2009-12-07 2014-04-16 STMicroelectronics (Research & Development) Limited Signal de balayage et transfert
EP2333830B1 (fr) 2009-12-07 2014-09-03 STMicroelectronics (Research & Development) Limited Un ensemble comprenant une première et une seconde matrice couplées par un bus multiplexé
EP2339475A1 (fr) * 2009-12-07 2011-06-29 STMicroelectronics (Research & Development) Limited Interface de communication inter-puce pour un boitier multi-puce
EP2339795B1 (fr) * 2009-12-07 2013-08-14 STMicroelectronics (Research & Development) Limited Interface de communication inter-puce pour un boitier multi-puce
EP2330514B1 (fr) 2009-12-07 2018-12-05 STMicroelectronics (Research & Development) Limited Paquet de circuits intégrés
US8959501B2 (en) * 2010-12-14 2015-02-17 Microsoft Corporation Type and length abstraction for data types
US8521937B2 (en) * 2011-02-16 2013-08-27 Stmicroelectronics (Grenoble 2) Sas Method and apparatus for interfacing multiple dies with mapping to modify source identity
US8836709B2 (en) * 2011-08-18 2014-09-16 International Business Machines Corporation Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline
CN102968379B (zh) * 2012-10-24 2015-05-06 无锡江南计算技术研究所 一种寄存器分配方法、系统及处理器
US20170199816A1 (en) * 2014-06-19 2017-07-13 Nec Corporation Information processing device, data storage method, and recording medium
US9818337B2 (en) * 2014-07-24 2017-11-14 Sct Technology, Ltd. LED display control circuit with PWM circuit for driving a plurality of LED channels
KR102446677B1 (ko) * 2015-11-26 2022-09-23 삼성전자주식회사 스토리지 컨트롤러의 동작 방법 및 상기 스토리지 컨트롤러를 포함하는 데이터 저장 장치의 동작 방법

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4349871A (en) * 1980-01-28 1982-09-14 Digital Equipment Corporation Duplicate tag store for cached multiprocessor system
US4300763A (en) * 1980-02-21 1981-11-17 Barr Samuel J Psychological game device
US4541046A (en) 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
US4394540A (en) 1981-05-18 1983-07-19 Timex Corporation Remote meter reader and method for reading meters over non-dedicated telephone lines
JPS6467680A (en) 1987-09-09 1989-03-14 Hitachi Ltd Vector processor
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
JP2570845B2 (ja) * 1988-05-27 1997-01-16 セイコーエプソン株式会社 情報処理装置
US5040109A (en) 1988-07-20 1991-08-13 Digital Equipment Corporation Efficient protocol for communicating between asychronous devices
US6070003A (en) 1989-11-17 2000-05-30 Texas Instruments Incorporated System and method of memory access in apparatus having plural processors and plural memories
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
JP2825906B2 (ja) * 1990-02-01 1998-11-18 株式会社日立製作所 計算機システム
US5263144A (en) 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5666510A (en) 1991-05-08 1997-09-09 Hitachi, Ltd. Data processing device having an expandable address space
US5530881A (en) * 1991-06-06 1996-06-25 Hitachi, Ltd. Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs
US5551010A (en) 1991-11-19 1996-08-27 Fujitsu Limited Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU
US5930522A (en) * 1992-02-14 1999-07-27 Theseus Research, Inc. Invocation architecture for generally concurrent process resolution
US5669010A (en) 1992-05-18 1997-09-16 Silicon Engines Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units
US5418973A (en) 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
US5423051A (en) * 1992-09-24 1995-06-06 International Business Machines Corporation Execution unit with an integrated vector operation capability
JP2765411B2 (ja) 1992-11-30 1998-06-18 株式会社日立製作所 仮想計算機方式
US5502683A (en) 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
US5546586A (en) 1993-05-06 1996-08-13 Apple Computer, Inc. Method and apparatus for vectorizing the contents of a read only memory device without modifying underlying source code
US5615343A (en) 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
US5644756A (en) 1995-04-07 1997-07-01 Motorola, Inc. Integrated circuit data processor with selectable routing of data accesses
US5822606A (en) 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5949439A (en) 1996-08-15 1999-09-07 Chromatic Research, Inc. Computing apparatus and operating method using software queues to improve graphics performance

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software

Also Published As

Publication number Publication date
CN1129078C (zh) 2003-11-26
CN1175037A (zh) 1998-03-04
JPH1091596A (ja) 1998-04-10
FR2752466A1 (fr) 1998-02-20
KR100280285B1 (ko) 2001-02-01
KR19980018069A (ko) 1998-06-05
DE19735981B4 (de) 2007-02-22
JP3954163B2 (ja) 2007-08-08
TW346573B (en) 1998-12-01
US6425054B1 (en) 2002-07-23
DE19735981A1 (de) 1998-03-26

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