FR2748855B1 - Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos - Google Patents

Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos

Info

Publication number
FR2748855B1
FR2748855B1 FR9606104A FR9606104A FR2748855B1 FR 2748855 B1 FR2748855 B1 FR 2748855B1 FR 9606104 A FR9606104 A FR 9606104A FR 9606104 A FR9606104 A FR 9606104A FR 2748855 B1 FR2748855 B1 FR 2748855B1
Authority
FR
France
Prior art keywords
manufacturing
protection device
overvoltage protection
cmos circuit
integrated cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9606104A
Other languages
English (en)
Other versions
FR2748855A1 (fr
Inventor
Richard Fournel
Fabrice Marinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9606104A priority Critical patent/FR2748855B1/fr
Priority to US08/854,840 priority patent/US5981323A/en
Publication of FR2748855A1 publication Critical patent/FR2748855A1/fr
Application granted granted Critical
Publication of FR2748855B1 publication Critical patent/FR2748855B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR9606104A 1996-05-15 1996-05-15 Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos Expired - Fee Related FR2748855B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9606104A FR2748855B1 (fr) 1996-05-15 1996-05-15 Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos
US08/854,840 US5981323A (en) 1996-05-15 1997-05-12 Method and apparatus for protecting a device against voltage surges

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9606104A FR2748855B1 (fr) 1996-05-15 1996-05-15 Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos

Publications (2)

Publication Number Publication Date
FR2748855A1 FR2748855A1 (fr) 1997-11-21
FR2748855B1 true FR2748855B1 (fr) 1998-07-10

Family

ID=9492188

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9606104A Expired - Fee Related FR2748855B1 (fr) 1996-05-15 1996-05-15 Procede de fabrication d'un dispositif de protection contre les surtensions pour un circuit integre cmos

Country Status (1)

Country Link
FR (1) FR2748855B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987465A (en) * 1987-01-29 1991-01-22 Advanced Micro Devices, Inc. Electro-static discharge protection device for CMOS integrated circuit inputs
EP0472654B1 (fr) * 1989-05-17 1997-10-08 Sarnoff Corporation Dispositif de retour a zero declenche par de faibles tensions
FR2649830B1 (fr) * 1989-07-13 1994-05-27 Sgs Thomson Microelectronics Structure de circuit integre cmos protege contre les decharges electrostatiques
US5369041A (en) * 1993-07-14 1994-11-29 Texas Instruments Incorporated Method for forming a silicon controlled rectifier
US5545910A (en) * 1994-04-13 1996-08-13 Winbond Electronics Corp. ESD proctection device

Also Published As

Publication number Publication date
FR2748855A1 (fr) 1997-11-21

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070131