FR2697103B1 - Procédé de test de mémoires et circuit mémoire associé. - Google Patents
Procédé de test de mémoires et circuit mémoire associé.Info
- Publication number
- FR2697103B1 FR2697103B1 FR9212489A FR9212489A FR2697103B1 FR 2697103 B1 FR2697103 B1 FR 2697103B1 FR 9212489 A FR9212489 A FR 9212489A FR 9212489 A FR9212489 A FR 9212489A FR 2697103 B1 FR2697103 B1 FR 2697103B1
- Authority
- FR
- France
- Prior art keywords
- test
- memories
- memory
- read
- test method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9212489A FR2697103B1 (fr) | 1992-10-19 | 1992-10-19 | Procédé de test de mémoires et circuit mémoire associé. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9212489A FR2697103B1 (fr) | 1992-10-19 | 1992-10-19 | Procédé de test de mémoires et circuit mémoire associé. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2697103A1 FR2697103A1 (fr) | 1994-04-22 |
| FR2697103B1 true FR2697103B1 (fr) | 1994-12-09 |
Family
ID=9434669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR9212489A Expired - Fee Related FR2697103B1 (fr) | 1992-10-19 | 1992-10-19 | Procédé de test de mémoires et circuit mémoire associé. |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2697103B1 (fr) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0263312A3 (fr) * | 1986-09-08 | 1989-04-26 | Kabushiki Kaisha Toshiba | Dispositif de mémoire semi-conductrice à fonction d'autotest |
-
1992
- 1992-10-19 FR FR9212489A patent/FR2697103B1/fr not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| FR2697103A1 (fr) | 1994-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |