FR2653912B1 - Circuit de garantie de zero pour un chemin de donnees ayant une largeur de bits differente de la longueur d'un operande decimal condense. - Google Patents

Circuit de garantie de zero pour un chemin de donnees ayant une largeur de bits differente de la longueur d'un operande decimal condense.

Info

Publication number
FR2653912B1
FR2653912B1 FR909013370A FR9013370A FR2653912B1 FR 2653912 B1 FR2653912 B1 FR 2653912B1 FR 909013370 A FR909013370 A FR 909013370A FR 9013370 A FR9013370 A FR 9013370A FR 2653912 B1 FR2653912 B1 FR 2653912B1
Authority
FR
France
Prior art keywords
warranty
condensed
zero
circuit
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR909013370A
Other languages
English (en)
Other versions
FR2653912A1 (fr
Inventor
Asano Sadaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2653912A1 publication Critical patent/FR2653912A1/fr
Application granted granted Critical
Publication of FR2653912B1 publication Critical patent/FR2653912B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Executing Machine-Instructions (AREA)
FR909013370A 1989-10-27 1990-10-29 Circuit de garantie de zero pour un chemin de donnees ayant une largeur de bits differente de la longueur d'un operande decimal condense. Expired - Fee Related FR2653912B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1281010A JP2504847B2 (ja) 1989-10-27 1989-10-27 １０進デ―タのチェック回路

Publications (2)

Publication Number Publication Date
FR2653912A1 FR2653912A1 (fr) 1991-05-03
FR2653912B1 true FR2653912B1 (fr) 1993-09-03

Family

ID=17633024

Family Applications (1)

Application Number Title Priority Date Filing Date
FR909013370A Expired - Fee Related FR2653912B1 (fr) 1989-10-27 1990-10-29 Circuit de garantie de zero pour un chemin de donnees ayant une largeur de bits differente de la longueur d'un operande decimal condense.

Country Status (3)

Country Link
US (1) US5274830A (fr)
JP (1) JP2504847B2 (fr)
FR (1) FR2653912B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341500A (en) * 1991-04-02 1994-08-23 Motorola, Inc. Data processor with combined static and dynamic masking of operand for breakpoint operation
US5319763A (en) * 1991-04-02 1994-06-07 Motorola, Inc. Data processor with concurrent static and dynamic masking of operand information and method therefor
US5479626A (en) * 1993-07-26 1995-12-26 Rockwell International Corporation Signal processor contexts with elemental and reserved group addressing
US5745744A (en) * 1995-10-12 1998-04-28 International Business Machines Corporation High speed mask generation using selection logic
US7373307B2 (en) * 2001-10-15 2008-05-13 Dell Products L.P. Computer system warranty upgrade method
US7373308B2 (en) * 2001-10-15 2008-05-13 Dell Products L.P. Computer system warranty upgrade method with configuration change detection feature
US11099853B2 (en) * 2019-02-15 2021-08-24 International Business Machines Corporation Digit validation check control in instruction execution

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51118344A (en) * 1975-04-11 1976-10-18 Hitachi Ltd Bit deticting system
US4021655A (en) * 1976-03-30 1977-05-03 International Business Machines Corporation Oversized data detection hardware for data processors which store data at variable length destinations
JPS5441035A (en) * 1977-09-08 1979-03-31 Nippon Gakki Seizo Kk Digital data converter circuit
JPS5743239A (en) * 1980-08-27 1982-03-11 Hitachi Ltd Data processor
JPS5743240A (en) * 1980-08-29 1982-03-11 Toshiba Corp Operating system with shift
US4384340A (en) * 1980-12-24 1983-05-17 Honeywell Information Systems Inc. Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions
JPS5824941A (ja) * 1981-08-07 1983-02-15 Hitachi Ltd 演算装置
JPS5827241A (ja) * 1981-08-12 1983-02-17 Hitachi Ltd 十進演算装置
US4615016A (en) * 1983-09-30 1986-09-30 Honeywell Information Systems Inc. Apparatus for performing simplified decimal multiplication by stripping leading zeroes
JPS6373325A (ja) * 1986-09-16 1988-04-02 Nec Corp 情報処理装置

Also Published As

Publication number Publication date
JPH03142533A (ja) 1991-06-18
JP2504847B2 (ja) 1996-06-05
FR2653912A1 (fr) 1991-05-03
US5274830A (en) 1993-12-28

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Legal Events

Date Code Title Description
ST Notification of lapse