FR2645665B1 - Dispositif de decodage d'instructions en pipeline pour microprocesseur - Google Patents

Dispositif de decodage d'instructions en pipeline pour microprocesseur

Info

Publication number
FR2645665B1
FR2645665B1 FR9004375A FR9004375A FR2645665B1 FR 2645665 B1 FR2645665 B1 FR 2645665B1 FR 9004375 A FR9004375 A FR 9004375A FR 9004375 A FR9004375 A FR 9004375A FR 2645665 B1 FR2645665 B1 FR 2645665B1
Authority
FR
France
Prior art keywords
microprocessor
decoding pipeline
pipeline instructions
instructions
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9004375A
Other languages
English (en)
Other versions
FR2645665A1 (fr
Inventor
Fu Beatrice
P. Gelsinger Patrick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2645665A1 publication Critical patent/FR2645665A1/fr
Application granted granted Critical
Publication of FR2645665B1 publication Critical patent/FR2645665B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
FR9004375A 1989-04-07 1990-04-05 Dispositif de decodage d'instructions en pipeline pour microprocesseur Expired - Fee Related FR2645665B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33518689A 1989-04-07 1989-04-07

Publications (2)

Publication Number Publication Date
FR2645665A1 FR2645665A1 (fr) 1990-10-12
FR2645665B1 true FR2645665B1 (fr) 1994-04-15

Family

ID=23310662

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9004375A Expired - Fee Related FR2645665B1 (fr) 1989-04-07 1990-04-05 Dispositif de decodage d'instructions en pipeline pour microprocesseur

Country Status (5)

Country Link
JP (1) JP2847316B2 (fr)
DE (1) DE4010895C2 (fr)
FR (1) FR2645665B1 (fr)
GB (1) GB2230116B (fr)
HK (1) HK56295A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
EP0663083B1 (fr) 1992-09-29 2000-12-20 Seiko Epson Corporation Systeme et procede pour la gestion des operations de chargement et/ou de stockage dans un microprocesseur superscalaire
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
DE69425310T2 (de) * 1993-10-18 2001-06-13 Via-Cyrix, Inc. Mikrosteuereinheit für einen superpipeline-superskalaren Mikroprozessor
US5794026A (en) * 1993-10-18 1998-08-11 National Semiconductor Microprocessor having expedited execution of condition dependent instructions
US5644741A (en) * 1993-10-18 1997-07-01 Cyrix Corporation Processor with single clock decode architecture employing single microROM

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629853A (en) * 1959-06-30 1971-12-21 Ibm Data-processing element
US4363091A (en) * 1978-01-31 1982-12-07 Intel Corporation Extended address, single and multiple bit microprocessor
CA1174370A (fr) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Unite de traitement de donnees avec operandes a traitement "pipeline"
US4573118A (en) * 1983-03-31 1986-02-25 Fairchild Camera & Instrument Corporation Microprocessor with branch control
US4574344A (en) * 1983-09-29 1986-03-04 Tandem Computers Incorporated Entry control store for enhanced CPU pipeline performance
US4812972A (en) * 1984-06-20 1989-03-14 Convex Computer Corporation Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions
JPH0776917B2 (ja) * 1984-12-29 1995-08-16 ソニー株式会社 マイクロコンピユ−タ
JP2554050B2 (ja) * 1986-02-26 1996-11-13 株式会社日立製作所 デ−タ処理方法
JPS62226231A (ja) * 1986-03-27 1987-10-05 Toshiba Corp プロセツサ
JPH0772863B2 (ja) * 1986-10-30 1995-08-02 日本電気株式会社 プログラムカウンタ相対アドレス計算方式

Also Published As

Publication number Publication date
GB2230116A (en) 1990-10-10
JP2847316B2 (ja) 1999-01-20
GB9003351D0 (en) 1990-04-11
DE4010895C2 (de) 1998-09-24
HK56295A (en) 1995-04-21
FR2645665A1 (fr) 1990-10-12
DE4010895A1 (de) 1990-10-11
JPH03201030A (ja) 1991-09-02
GB2230116B (en) 1993-02-17

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Legal Events

Date Code Title Description
ST Notification of lapse