FR2629285A1 - METHOD OF SERIAL TRANSMISSION OF SWITCHING STATES - Google Patents

Abstract

By a method of rapid serial transmission, by cable, of the switching states of several switches located on an operating circuit, very few connecting lines must be obtained between a compact transmission circuit, close to the switches, and a circuit operating with high transmission security. The operating circuit 9 conducts the clock pulse cycles to the transmission circuit 3. The switching states are applied to a single data transmission line 8 by means of the clock pulses. For one of the clock pulses, a third state is applied to the data transmission line 8, entering the operating circuit 9.

Description

Method of serial transmission of switching states The invention

  a serial cable transmission method of the switching state of several switches, in particular switches of the brush handle of an aircraft, on an operating circuit, the switches being placed in a

  matrix of a transmission circuit.

  In order to transmit switch switching states from a joystick of an aircraft to an operating circuit, it is desirable to have a serial data transmission, since parallel transmission would require plurality of links between the switches and the operating circuit. For an asynchronous, serial transmission, an own oscillator of synchronization would be necessary in the operating circuit and in the transmission circuit. Due to the confined conditions of space in the broom handle, however, it can not be provided inside a synchronization oscillator having a stability or a safety of

sufficient operation.

  It is disadvantageous to provide for a known synchronous, serial transmission of the data, since if it must be sufficiently safe, it must work

comparatively slowly.

  The object of the invention is to provide a method of the type indicated at the beginning, requiring few connecting lines and little room for switches, for a transmission security

high.

  According to the invention, the above problem is solved for a method of the type indicated at the beginning, in that clock pulse cycles are transmitted from the operating circuit to a transmission circuit via a synchronization line, in that the pulses cyclically interrogate the switching states of the switches one after the other and apply them to the operating circuit, via a single data transmission line, in that for, a certain clock pulse of each clock pulse cycle, a third state is applied in a transmission circuit to the data transmission line, and in that the operating circuit is seized by a circuit control that detects if the third state only occurs for the determined clock pulse, and then deletes the data received during this cycle, if

  the third state occurs at another time.

  A single synchronization line and a data transmission line are required between the transmission circuit disposed near the switches and the operating circuit remote therefrom to effect transmission of the switching states. The switching states of the switches are scanned one after another during the synchronized period of the clock pulses. A third state is transmitted by the transmission circuit to the operating circuit, during a single clock pulse of each clock pulse cycle is transmitted. Unlike the H (high) or L (low) level of the data transmission line, this represents a strongly resistive resistance, discerned by the operating circuit. By the control pulses arriving on the synchronization line it can lead to a displacement of the assignment existing between the switch concerned and the clock pulse that scanned it, which would correspond to a confusion between the switches. However, since in this case the third state has also been moved, which does not appear during the determined clock pulse, the operating circuit can discern this displacement and delete the data.

  transmitted in a disturbed cycle.

  Short-circuit and breaks in the synchronization line and the data transmission line

  are also discernable by the operating circuit.

  The transmission circuit can be housed saving space in the joystick because it

  does not have any own oscillator.

  According to one characteristic of the invention, the clock pulses are applied to a counter of the

transmission line.

  According to a characteristic of the invention, a mutiplexer is placed on the rows of the columns of the matrix, and the data transmission line is connected to it and a demultiplexer is placed on the lines of the rows of the matrix and the demultiplexer as well as the multiplexer are switched by the clock pulses,

through the meter.

  According to another characteristic of the invention, a controllable tri-state output stage is connected in the transmission circuit, before the data transmission line, and is switched to the third state for a

some clock pulse.

  According to another characteristic of the invention, the tri-state output stage is controlled by the counter. According to another characteristic of the invention, the control circuit of the third state of the data transmission line is operated by a resistor placed at the high or low potential of the synchronization line. Various other features and advantages of

  device the invention stand out from the description

  detailed below. One embodiment of the invention is shown by way of nonlimiting example in the accompanying drawings in which: FIG. 1 represents a block diagram of an overall circuit comprising a transmission circuit, transmission sections and a circuit. operating; Figure 2 shows a block diagram of a construction element of the transmission circuit; FIG. 3 represents a matrix of the transmission circuit, connected to the construction element of FIG. 2;

  Figure 4a shows a switching diagram.

  On a broomstick not shown, in the case of the example, up to 24 switches S1 to S24 are provided, which, however, can be increased at will. Each switch has a manually operated switching contact 1 which switches a transistor TR. The transistors TR are connected in circuit in a matrix 2 (see FIGS. 1 and 3). This has six lines QA to QF for the rows and four rows IA to ID for the columns. Resistors R1 to R4 are placed

  on lines IA to ID for columns.

  The matrix 2, comprising a structural group 4 and filters 5, 6, is part of a transmission circuit

  3 arranged in the control handle.

  The transmission circuit 3 is connected to an operating circuit 9 via a synchronization line 7 on which the filter 5 is placed and a data transmission line 8. The synchronization line 7 and the data transmission line 8

  form the transmission section.

  A grounding circuit 10 and a voltage supply line 11, in which the filter 6 is placed, are furthermore developed between the

  transmission 3 and the operating circuit 9.

  The operating circuit 9 has an operating computer 12, whose clock output is connected to a low ohmic output via a pilot oscillator / serving to improve the resistance to disturbances of the synchronization line 7 The data transmission line 8 is connected, via a filter 14 and a Schmidt trigger 15 of a control circuit 16, to a data input of the operating calculator 12. An output 18 of the operating computer 12 is further placed at the input of the Schmidt trigger 15, via a resistor R5 and a driver 17. The output 18 is placed in the normal case at low level. R5 works in "pull down" resistance or zero resistance. When changing from high to low,

  at the data input, the output 18 goes from low to high.

  Resistance R5 is now working in pull resistance

  up ", otherwise known as work resistance.

  An output unit 19 is connected to the calculator

  12 to deliver the data in parallel.

  A succession of clock pulses applied by the evaluation computer 12 to the synchronization line 7 comprises 32 bits. The structural group 4 of the transmission circuit 3 has a positive 5-bit counter 20, so that 32 different combinations are possible. Since in this case no more than 24 switches are provided, the remaining count states

  can be exploited for other purposes.

  The counter 20 is triggered by a flank of the clock pulses. Its five outputs A to E are connected to a six-way demultiplexer 21, to which the six lines QA to QF for the lines are applied. The demultiplexer has the property that there is always one of its outputs at the value "1", while the other outputs remain at the value "0" (see Figure 4). The five outputs of the counter 20 are also applied to a four-way multiplexer 22, at the inputs of which are connected the four lines IA to ID for the columns. The multiplexer 22 has the property of always only switching one of its four inputs on the line of

data transmission 8.

  A tri-state output stage 23, controllable and controlled by a synchronous mark decoder 24, is connected to the output of the multiplexer 22. The outputs of the counter 20 are also applied thereto. For bits 1 to 24 (see FIG. 4), which correspond to the counter states 0 to 23 of the counter 20, the synchronous mark decoder 24 switches the tri-state output stage 23 so that the output signal of the multiplexer 22 is inverted on the data transmission line 8. A high or low level is applied to the data transmission line 8 as a function of the switch S1 to S24 called to react via the demultiplexer 21 and the multiplexer 22 and the switching state of this switch. In the case of a value bit 32, the decoder 24 switches the tri-state output stage 23 into its third state, thus representing a strongly ohmic resistance of the data transmission line 8, unlike the state. up or down. This state is represented by zzz in FIG. 4; Essentially, the operating mode of the described circuit is as follows: The line Qa is switched on high by the rank 1 to 5 clock pulse at each clock pulse cycle via the counter 20 and the demultiplexer 21. As a result, the line QB is switched hard high from the 5th to the 9th clock pulse. This continues until the QF line has been switched to high, from the 2nd to the 25th pulse

clock (see Figure 4).

  If, for example, the switch S3, located between the line line QA and the column line IC, is closed during the third clock pulse, the multiplexer 22 is then switched by the counter 20 on the column line IC, a low signal is then applied to the data transmission line 8 via the resistor R3 and the tri-state output stage 23 (see FIG. 4). In the case shown in FIG.

  in addition to the switch S3, the switch S24 is actuated.

  If, during the presence of the high signal on the line QA, besides the switch S3, there is also one or more switches closed, among Si, S2 or S4, this has no effect on the signal acting on the line of transmission of data 8. In the case where there has been no scanning or activated switches, it is a

  high potential that is present on the data line 8.

  This scanning of the switching states has, in comparison with a scan carried out by means of drawer registers, the important advantage that the structural group 4 does not require a connection of its own.

each switch Si to S24.

  The serial data stream of the data transmission line 8 arrives at the Schmidt 15 trigger.

  operating calculator 12 discerns by the high jumps

  during its 3rd and 24th clock pulses, the switches S3 to S24 are closed, that is to say actuated, and delivers, in the case of absence of disturbances, signals corresponding to the unit of

exit 19.

  At each 32 th clock pulse on the data transmission line 8 there occurs the tri-state switched by the three state output stage 23. Due to the low potential applied to the resistor R5 through the output 18, the trigger input of Schmidt 15 is from this

moved to low potential.

  If this occurs during the 32nd clock pulse, the operating computer 12 discerns whether there is then coincidence of the synchronization and thus the relationship between each switch scrutinized and its switching state received. After each level change, from top to bottom, the operating computer 12 switches its output 18 from low to high. This does not influence the input of the Schmidt trigger 15 as long as there is a high or low potential on the data transmission line 8. At the end of a third state, however, the resistor R5 brings the input Schmidt trigger 15 at high potential (characteristic of "working resistance"). The operating calculator 12 takes this as the

synchronization present.

  Exit 18 is as a result of this switched to

again on low.

  If a line break occurs, it corresponds to a third state, but no longer occurs during the 32nd clock pulse, but in a lasting manner. The operating calculator 12 enters this. If a short circuit occurs against one potential or another, the third state can no longer be established. The operating calculator 12 can

also grab this.

  Other clock pulses occur between the last clock pulse, the 24th, which is provided for the switch scanning, and the 2nd clock pulse, which is provided for the third state. They can be exploited for other control information. For example, it is also possible to use one of these clock pulses as a test for a state of short circuit or line breaking.

  and pass this on the Schmidt trigger 15.

  If there is a line break, the high potential of this clock pulse can not be coupled. If there is a short circuit with respect to the high potential, the low potential of this clock pulse can not be coupled. If there is a short circuit with respect to the low potential, the high potential of this clock pulse can not appear on the Schmidt trigger 15.

Claims (6)

  1. A method of serial cable transmission of the switching state of several switches, in particular switches of a brush handle of an aircraft, on an operating circuit, the switches being placed in a matrix of a transmission circuit, characterized in that clock pulse cycles are transmitted from the operating circuit (9) to a transmission circuit (3) via a synchronization line (7), the pulses cyclically interrogate the switching states of the switches (S1 to S24) one after the other and apply them to the operating circuit (9) via a single data transmission line (8). in that for a certain clock pulse (32) of each clock pulse cycle, a third state is applied in a transmission circuit (3) to the data transmission line (8), and in that the operating circuit (9) is grasped by a control circuit (16) detecting if the third state only occurs for the determined clock pulse (32), and then deletes the data received in that cycle, if the   third state occurs at another time.   2. Method according to claim 1, characterized in that the clock pulses are applied to a   counter (20) of the transmission line (3).   3. Method according to claim 2, characterized in that a mutiplexer (22) is placed on the rows of the columns (IA to ID) of the matrix (2), and that the data transmission line (8) is connected and in that a demultiplexer (21) is placed on the lines of lines (QA to QF) of the matrix (2) and that the demultiplexer (22) and the multiplexer (21) are switched by the   clock pulses, through the counter (20).   4. Method according to any one of the claims   preceding, characterized in that a controllable tri-state output stage (23) is connected in the transmission circuit (3), before the data transmission line (8), and is switched to the third state for a some clock pulse.   5. Process according to any one of the claims   2 to 6, characterized in that the output stage at three   states (23) is controlled by the counter (20).   6. Process according to any one of the claims   preceding, characterized in that the control circuit (16) of the third state of the data transmission line (8) is operated by a resistor (R5) placed at the   high or low potential of the synchronization line.