FR2611286B1 - Circuit integre multiplieur, et son procede de composition - Google Patents

Circuit integre multiplieur, et son procede de composition

Info

Publication number
FR2611286B1
FR2611286B1 FR8702328A FR8702328A FR2611286B1 FR 2611286 B1 FR2611286 B1 FR 2611286B1 FR 8702328 A FR8702328 A FR 8702328A FR 8702328 A FR8702328 A FR 8702328A FR 2611286 B1 FR2611286 B1 FR 2611286B1
Authority
FR
France
Prior art keywords
integrated circuit
composition method
multiplier integrated
multiplier
composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8702328A
Other languages
English (en)
Other versions
FR2611286A1 (fr
Inventor
Andre Bosset
Pascal Moulen
Philippe Pauchard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Dassault Electronique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dassault Electronique SA filed Critical Dassault Electronique SA
Priority to FR8702328A priority Critical patent/FR2611286B1/fr
Publication of FR2611286A1 publication Critical patent/FR2611286A1/fr
Application granted granted Critical
Publication of FR2611286B1 publication Critical patent/FR2611286B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR8702328A 1987-02-23 1987-02-23 Circuit integre multiplieur, et son procede de composition Expired FR2611286B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8702328A FR2611286B1 (fr) 1987-02-23 1987-02-23 Circuit integre multiplieur, et son procede de composition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8702328A FR2611286B1 (fr) 1987-02-23 1987-02-23 Circuit integre multiplieur, et son procede de composition

Publications (2)

Publication Number Publication Date
FR2611286A1 FR2611286A1 (fr) 1988-08-26
FR2611286B1 true FR2611286B1 (fr) 1989-04-21

Family

ID=9348182

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8702328A Expired FR2611286B1 (fr) 1987-02-23 1987-02-23 Circuit integre multiplieur, et son procede de composition

Country Status (1)

Country Link
FR (1) FR2611286B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650088A1 (fr) * 1989-07-18 1991-01-25 Thomson Csf Procede pour la generation de schemas logiques de circuits multiplieurs parametrables a decodeur de booth au moyen d'un ordinateur et circuits multiplieurs correspondants
JP3678512B2 (ja) * 1996-08-29 2005-08-03 富士通株式会社 乗算回路、該乗算回路を構成する加算回路、該乗算回路の部分積ビット圧縮方法、および、該乗算回路を適用した大規模半導体集積回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2544105B1 (fr) * 1983-04-06 1988-10-14 Thomson Csf Multiplieur du type en cascade utilisant un ensemble d'operateurs elementaires
FR2545957A1 (en) * 1983-05-10 1984-11-16 Efcis High-throughput binary multiplier
US4748582A (en) * 1985-06-19 1988-05-31 Advanced Micro Devices, Inc. Parallel multiplier array with foreshortened sign extension

Also Published As

Publication number Publication date
FR2611286A1 (fr) 1988-08-26

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