FR2572234A1 - POTENTIAL OFFSET DEVICE FOR GAAS INTEGRATED CIRCUITS - Google Patents

Abstract

THE INVENTION CONCERNS DIGITAL INTEGRATED CIRCUITS IN GAAS USING MESFET TRANSISTORS WITH DEPLETION MODE. INTEGRATED CIRCUITS IN ACCORDANCE WITH THE INVENTION USE A FET LOGIC WITH CAPACITOR AND DIODE COUPLING WHICH IS OPTIMIZED WITH REGARD TO PERFORMANCE AND EASE OF MANUFACTURING, WHILE MAINTAINING LOW CONSUMPTION. A STRUCTURE CONFORMING TO THE INVENTION INCLUDES IN PARALLEL A CHAIN OF POLARIZATION DIODES 12, 14, 16 ON A CAPACITIVE ELEMENT 10 CONSTITUTED BY A SCHOTTKY DIODE, AND THIS PARALLEL COMBINATION IS CONNECTED IN SERIES WITH A CURRENT ABSORPTION ELEMENT 18 , SO AS TO ESTABLISH A DEFINED VOLTAGE OFFSET BETWEEN AN INPUT AND AN OUTPUT OF AN INTEGRATED CIRCUIT. APPLICATION TO HIGH-SPEED INTEGRATED CIRCUITS.

Description

The present invention relates to a logic circuit with FET coupling

  capacitor and diode for circuits

  integrated D-MESFET GaAs.

  Historically, the most difficult problem in the design of MESFET GaAs depletion mode ICs has been to realize the shift function of

  necessary level between the positive drain voltage required

  the operation of these N-channel D-MESFETs, and the negative gate voltages necessary to block other D-MESFETs. In contrast, in the direct coupled FET (DCFL) logic, the gate inputs of the enhancement mode FETs are connected directly to the drain outputs. Transient gate output current

  available to attack a characteristic capacitive load

  tive is, in operation in current source,

  basically equal to the current of an active load connected

  at the positive supply voltage, which is equal to the

  continuous power supply, and in the operation of

  current sink, this output current transi-

  can be several times this value. Generally speaking

  However, none of the published structures of D-MESFET circuits approach a DCFL logic output (defined by the

  ratio between the charging current that can be achieved

  hold and the power supply), although they are superior in simplicity. On the other hand,

  enrichment mode FETs available in GaAs (E-

  MESFET, E-JFET and E-HEMT) are affected by important

  problems of manufacturing aptitude, centered

  on their limited grid trips (eVLest

  approximately 500 mV in E-MESFET type DCFL circuits), and on the correlative gate threshold voltage command that these excursions require (OVp must be less than or equal to VL / 20 to obtain a good manufacturing efficiency and good performance in circuits

  high level of integration and at a very high level of integration

  which corresponds to approximately 25 mV in

  logy = E-MESFET). D-MESFET technology uses more

  large excursions of logical voltage (AVL is

  approximately 1V to 2V in logic circuits D-MESFET), so that the required uniformity, OVp, is approximately 50 to 100 mV on

  a chip, which is a very valuable value

  in manufacturing with manufacturing technology

  current GaAs integrated circuits.

  Although the ease of manufacture and the speed

  its higher D-MESFET integrated circuits to GaAs

  these very interesting circuits, the realization of the

  voltage shift function in most structures

  The described D-MESFET circuits have led to binding compromises in terms of performance and / or energy efficiency. In the original logic structure of FET with a buffer function (BFL) proposed by Hewlett-Packard (see R. L. VanTuyl's article, C. A. Liechti, R. E. Lee, and E. Gowen, IEEE JSSC, SC-12, pp.

  485, 1977), the shift was made in an output stage.

  with a separate common drain, which gave rise to a possibility

  maximum current absorption capacity of approximately 60%

  of the feed stream, and resulted in a number of

  loss of speed due to delay in the output stage.

  In later work by Hewlett-Packard, using weakly loaded mice, the floor was removed.

  common drain in favor of a direct chain of 3 diodes

  to an element connected to the negative supply voltage (having about half the width of the load

  active connected to the positive supply voltage). This-

  logic to FET "without buffering element", or BLFL (see

  article by Barna, A. and CA Liechti, "Optimization of GaAs MESFET Logic Gates with Subnanosecond Propagation Delays," IEEE Journal of Solid-State Circuits, SC-14, August 1979) resulted in smaller delays for queues. low, but the current efficiency was still

  about 50% (the output could supply or absorb

  about 50% of the feed stream), and the energy efficiency

  The geometry was still lower because, as in the BFL structure, this high current flows to -VEE and not to Vss (the mass in the BFL structure). This FET logic "without buffer" also brings up another problem which is that of the current subtraction. The

  available charging current is the difference between a

  high power directed to the positive power terminal and

  high current directed to the negative power supply terminal

  ve, so that if the ratio between currents changes

  (eg because of statistical variations in

  or the back gate effect), the available charging current is strongly affected. This problem is even more serious in the Schottky diode FET logic, SDFL (see U.S. Patent No. 4,300,064 and Reference 3, US Pat.

  R. C. Eden, B. M. Welch, R. Zucca and S. I. Long, IEEE Tran.

  Electron Devices, ED-26, No. 4, pp. 299-317 (1979) or SC-14,

  No. 2, pages 221-239 (1979)) in which, because of the use

  In the case of diode logic, the load connected to the negative supply voltage is high, and is in fact variable depending on the outgoing and the logic state of other door inputs in the doors constituting the load. . From the point of view of current efficiency, the logic

  Conductively Coupled FET or CCFL (see Commission Notice).

  A. Livingstone and J. T. Mellor "Capacitor

  Coupling of GaAs Mode Depletion FET's "1980 GaAs IC Sympo-

  sium Abstracts, communication N 10) is excellent (appro-

  approximately identical to the DCFL logic), and allows operation with a single power supply, but the doors

  in CCFL logic can not operate in current

  tinu, which is usually unacceptable in

  logical complications. In addition, the described CCFL circuits use reverse biased Schottky diodes which are

  manufactured on the n-channel of the FET channel, for

  coupling densifiers. At the corresponding inverse polarization

  the normal operation of these capacitors constitutes

  When diode-killed, this layer is pinched, so that the capacitor structure is very complex and misuses the available area. A somewhat similar operation has been obtained, but extended to the steady state, by adding an action capacitor to

  downstream to the BFL door structure, thus giving the structure

  FF-BFL (see the article by R. Namordi and W. A.

  White, IEEE Electron Device Letters, V.EDL-3, N 9, September

  1982, pages 264-267), but at the cost of an important sacrifice

  both in terms of current efficiency and

  plexity, because of the common drain outlet stage.

  The invention relates to the use of a capacitor-coupled diode (CDFL) logic gate structure for the design of logic circuits of the D-MESFET type.

  GaAs, which allows operation from

  run to very high speeds with a current efficiency of 90% to 97% typical value (CDFL logic gates can supply about 90% to 97% of the supply current and absorb a current of up to several times this value). In addition, this structure does not require the complication of a common drain outlet stage in each door. The CDFL structure is based on the recognition that in a logic with FET, the

  Charging currents are essentially capacitive. This if

  that the best voltage shifting element would be a small built-in battery on the chip between the drains

  D-MESFETs to the logical node at FET and the output of the gate.

  In the case of pure capacitive loads, such a battery must not provide any resulting continuous power and, in

  fact, if the MESFET grids connected to the output do not

  occasionally in the state of direct conduction, the

  battery charging instead of discharging. In the soul-

  sure that such battles are not available at the moment.

  in integrated circuits, it is desirable to use

  bend an appropriate replacement element, also having minimum power or complexity requirements. The object of the invention is therefore to provide a constant voltage offset circuit for circuits

  integrated in GaAs which improves yields in terms of

  encodes the charging current without causing a significant signal delay and is of acceptable size (i.e., does not excessively reduce the door density of the

  integrated circuits). The invention further aims to pro-

  a number of specific circuit techniques for D-MESFET logic gates, including fixing the drain to a "high" level by Schottky diode and fixing

  from the drain to a "low" level by saturation diode,

  to further improve logical delays or transition speeds. In addition, the invention aims to present input circuits using techniques

  Schottky diode level fixation and resistance

  in saturation, in association with the shift of

  level in the CDFL logic, which offer both a

  against excessive heat destruction in

  the presence of logical input signals exceeding

  the normal levels, and precise control of the input threshold voltage (even if the

  of a MESFET is changed because of variations in the

  manufacturing process), so as to ensure compatibility

  signals with logic circuits with transmission coupling

  Bipolar Silicon Type ECLs. A

  Another aim is to present techniques concerning

  Output circuits using Schottky diode "high" level fixation and "low" level

  saturation diode on the grid input of a device

  common drain output, allowing the con-

  the possibility of performing a wired OR function, as well as a well-defined compatibility of output signals with ECL logic over a wide range of combinations of

  load resistance and termination voltage.

  The invention will be better understood on reading the

  description which will follow of modes of realization, and

  Referring to the accompanying drawings in which: Figure 1 shows a voltage shift circuit in CDFL logic, Figure 2 shows a characteristic NOR gate circuit in CDFL logic, with a CDFL type output level shift circuit, and FIG. 3 represents an input / output circuit

  CDFL compatible with ECL logic, for a local inverter

  cal. Referring now to FIG. 1, it will be noted that a capacitor-coupled diode FET logic (CDFL) uses the level shifter structure of FIG. 1 as a sufficiently close replacement element for the mentioned ideal battery. previously. The circuit comprises a capacitor called DCAP, 10, which is held charged at a substantially constant voltage, VDECALAGE 'by a very small current flowing in a chain formed by three small Schottky diodes 12, 14 and 16. The low bias current is provided by a

  current absorbing element PD, 18, of very low

  When connected to a negative supply voltage, VEE (VEE must be more negative than the most negative output logic output, with a deviation of approximately one volt or more, when using for PD element 18 D-MESFETs having a blocking voltage V = -1.0 V). In addition, ITD is approximately equal to I polarity. Correct operation of the level shift circuit of FIG. 1 is obtained when the capacitance of the DCAP shift capacitor 10 is much greater than the load capacitance 20 (typically times CCHARGE). Under these conditions, almost all of the input AC current flows to the load and the

  gain in alternating voltage and high frequency of the circuit

  shifted AVL / AVIN = CDCAP / (CCHARGE + CDCAP); approaching the unit (from 0.75 to over 0.9) Although other capacitor structures can be used

  (like metal-insulator-metal (MIM) capacitors to

  high mitigation) to realize the DCAP capacitor, a special reverse biased Schottky diode structure having a high C / A value (capacitance divided by area) is used in the present circuits. We manufacture this

  device on a relatively doped implanted layer.

  strong (> 2 X 1017 / cm2), having sufficient thickness

  not to be pinched to the corresponding reverse polarization

  during normal operation (VDECALAGE is approximately

  volts with a 3 diode offset circuit). We can also

  increase the capacitance of the DCAP capacitor, without

  additional summation of the area of the chip, by placing in parallel on the capacity of the diode the MIM capacitance of an additional electrode consisting of a metal layer of the second level, connected to the cathode of the diode and extending over the metal of the anode of the Schottky diode,

  but being separated by a thin dielectric layer.

  This basic level shift circuit structure 22 may be used at any point in circuits in which a level shift is required; in input / output (I / O) circuits, on door entrances, on door exits, etc. Fig. 2 shows a simple 3-input NOR gate structure in CDFL logic, using a CDFL type output level shift circuit. It is also possible to place CDFL level shifters equally at each gate entrance, so that

  It is not necessary to attack the lines of information

  tconnection via the DCAP capacitor 29, which provides a smaller area for the DCAP capacitor 29, but this requires a greater number of level shift structures to be made, because the number of gate inputs is typically several times greater than the number of door exits. The three parallel-connected MESFETs 24, 26, and 28, used to perform the NOR function in FIG. 2, illustrate a CDFL gate configuration. In general, various serial-parallel combinations of D-MESFET can be used to perform different CDFL logic functions, as in other types of FET logic. The use of dual gate FETs or serial and parallel FET combinations to realize different logic functions in a FET logic gate is familiar to those skilled in the art, as is the use of other types of devices. such as saturating resistors, gateless FETs, resistors or combinations of these elements

  with FETs, for the load connected to the supply voltage

  33, and / or the load connected to the voltage

  negative power supply, 35 (or 18 in Figure 1 or 56, 58 or 60 in Figure 3). This circuit is represented

  with the usual feeding potentials for a function

  compatible with ECL logic (VDDL = MASS, VEE = -5.2 V as for conventional ECL power supplies, plus here a VSS = -3.3 V). In a more usual operation of a GaAs integrated circuit,

  we would have Vss = MASS, VEE = -1.9 V (or a higher value).

  gative) and VDDL = +3.3 V (or a more positive value). This circuit, with the particular dimensions indicated for the FETs, requires a maximum supply current of (IDSS / W.) X 16.5 micrometers (W = GRID WIDTH), while it can supply up to (IDSS / W) X (16.5-1.5 micrometers) = 15 nm,

  so that the current efficiency (for the operation

  current source) is 15 / 16.5 = 91%. The return

  operating current as an absorption element of

  current, expressed as a percentage, may be several

  some (depending on the maximum input voltage), even

from a single entry.

  The NAND or CDFL gate structure of Figure 2 also illustrates another technique developed for

  GaAs, to maintain fast performance.

  optimal performance over a wide range of power supply voltages.

  tation (VDDL-Vss = 3.3 to 7 volts), if desired. In logical structures with normal FETs, the high side logic excursion is limited by the positive supply voltage (VDDL-Vss), by the "progressive limitation" action of a

  active load connected to the positive supply voltage

  ve, PU, which passes out of the state of saturation of the drain.

  When increasing (VDDL-Vss), the positive logic excursion increases to the point where the Schottky grids of the

  MESFET charge go into a state of strong conduction.

  This last condition places MESFETs in a region

  in which the parameter f. is extremely

  poorly (C grid capacity very high, with gs

  a bad transconductance, gm), which degrades people

  beyond the degradation that is produced by the excessive logic voltage excursion itself (the switching transition time of a capacitive load, C ,, with a constant load current, IL, switching on an excursion AVL logic voltage, is approximately t = CL MVL / IL). The use of an optional Schottky switching diode, 30, DLCH, providing a

  logical level to a high level which corresponds to a potential

  VLCH securing device, ensures an abrupt limitation of the positive logic excursion, independently of VDDL-Vss, which avoids this degradation of the performances under the effect of a variation of the power supply voltage (i.e. say an increase in AVL when VDDL increases). We can

  get the VLCH potential from a not-power supply

  sive (for example a Zener diode alone), since this power supply only absorbs current directed towards VSS. One can establish on the chip a diet comprising

  a current-absorbing voltage regulator for supplying

  denote a VLCH nominal level setting potential.

  A point of less importance but offering a

  some possibility of improving performance,

  use of the optional VLCL input 32 to better control the logic excursions by setting the low logic level by means of the optional diode 34. In addition to decreasing the delay by decreasing AVL, this has the effect of keep the MESFETs out of the region with very low VDS (at high Vgs) in which the parameter fC is bad. This leveling however requires an active power supply (energy source) and therefore increases the dissipation of the door. This could in practice prevent the use of VLCL, if this use was

  in a simplistic way, because if the three MESFETs

  24, 26 and 28 in the door of Figure 2 were all placed in the conducting state with Vg = 0.8 V, the resulting total drain current gs could, with a steep level fixing, reach 10 times the current active charge

  connected to the positive supply voltage (PU), IDD-

  This condition is avoided by the use of a special Schottky diode structure 34 of the saturation type by the

  speed, for the DLCL diode, which goes into a state of limi-

  controlled current when the direct current exceeds

  to a specified level. This avoids the occurrence of excessive current for VLcL when a large number of logical FETs connected in parallel are simultaneously in the conducting state (for example FETs 24, 26 and 28 in FIG. 2), but

  always ensures optimal logical operation in

  very quickly the logical level low to its correct value.

  when some of the entrances to the door are

  cated. The saturation-rate diode used for the DLCL element 34 (as well as for the DDCL element 61 on it

  FIG. 3) is a flat Schottky diode structure used

  + reading the same implanted n-type layer (employing the same technology as in Reference 3), as Schottky switching-level setting diodes (for example in FIG. 2 and 40, 42 or 62 in FIG. ). These saturation diodes, however, are designed by carefully defining the periphery of the anode of the diode (Schottky contact), in order to define the maximum direct current, and they are also designed so that the current that

  circulates in the metal contacts for this value of the neck.

  direct saturation does not exceed the migration limit.

  metal for the interconnect metal used (JMAx is approximately 1 X 106 A / cm for gold). The direct saturation current of the saturation diode by the

  speed, 34 or 61, is fundamentally proportional to the

  the anode of the diode (perimeter of the Schottky contact that is actually in contact with the implanted layer of + type n), and the proportionality constant is about

  1 mA of saturation direct current per micrometer of

  anode meter, for n + characteristic implanted layers having a square resistance of approximately 450 1 which is used for Schottky switching diodes in GaAs integrated circuits. In some applications, the modest speed improvements provided by using VLCL do not justify the increased complexity that results

  the establishment of the input source potential input of

  addition, and the additional dissipation

  (although relatively weak) that appears on the chip, so that one can remove the diode DLCL 34. If this diode is incorporated, one can use a connection

  shutdown between VLCL and VSS.

  Although a basic gate structure such as the NAND or CDFL gate shown in FIG.

  FIG. 2 to efficiently perform logic functions.

  In such circuits, such a structure will not generally be

  can not be used for

  trea and output of a chip. It is frequently required that GaAs digital integrated circuit outputs drive transmission line impedances with conventional ECL signal levels, while the inputs must be compatible with ECL signals and must also withstand deterioration under the ECL signals. effect of signals exceeding

  considerably the normal levels, under the effect of

  static, etc. Figure 3 shows a structure of inversion

  which includes both the CDFL input and output configurations. The inverter circuit 36 which is shown is

  unusual in that input and output circuits are

  embedded in the chip are in the same stage (in most chips, these circuits are separated by a number of logical stages), but the principles of

I / O circuits are the same.

  Signal inputs are protected by a

  Bidirectional current source SATR '(saturation resistor

  or D-MESFET without grid), 38, and by a combination of diode

  DICH (High Input Level Diode) 40 and DICL (Low Input Mount Diode) 42, which provide steady-state AC signal levels of up to 30 degrees. 'at about

  peak-to-peak volts (+40 dBm), without deterioration or

  turbation of the correct operation of the circuit. The SATR device 38 has a low resistance of 30 to 40 ohms for low (normal) applied voltages, but for applied voltages greater than about +1 V, the device

  goes into current limitation with an Isat of about +10 mA.

  (The SATR device can be manufactured in the same way as a D-MESFET in most GaAs integrated circuit manufacturing processes using D-MESFETs, but by removing the Schottky gate electrode that would be found

  normally above channel n, between the source regions

  this and implanted n-type drain.) This current limiter

  bi-directional "FET without grid" has been de-

  written in documents concerning GaAs integrated circuits. For a single input protection, it is possible to use level setting voltages taken by default with the following values: VIcH = VDDL = 0.0V (GND) and VIcL = V s = -3.3V, which limits the voltages signal levels within a safe range (but over normal levels) from +1.2 to -4.5 volts. We can also use

  conveniently this input structure to generate

  "squared" internal signal signals from unregulated sinusoidal signal sources. This conversion is usually done in square signals by applying VIcH = V ICL =

  -, 3V (the threshold of ECL signals), using in a typical way

  characteristic of a blocking capacitor in the line of

  input signal to suppress any DC component, and then applying a sinusoidal input signal of 3 VDC to 20 VC (+13 dBm to +30 dBm) to give an internal "square" DC signal of about 2 V0c (-0.3V to -2V), With normal input signal levels of -0.8V to -1.8V, the SATR 38 device has virtually no effect on performance. because of its weak resistance (it introduces

  typically a delay of 5 ps).

  The key problem from the point of view of input is to maintain the appropriate input threshold voltage of

  -1,3 V, Vth, for compatible operation with

  ECL signals over the D-MESFET blocking voltage range

  usually encountered in the manufacture of

  embedded GaAs (exceeding Vp = -1.0 + 0.2 V). The

  key to controlling the threshold voltage lies in the use of

  the fact that short-distance variations of V (variations of V measured at distances less than

P P

  a gap of about 1 mm) are weak in contrast to

  variations from one slice to another which are the largest (with small gradations on neighboring slices) o Because

  the element connected to the supply voltage

  positive (PU) 60 and switching FET 44 have

  unequal values, the gate voltage V -Vss at the threshold is g ss different from zero (Vg -Vss is approximately equal to 1d / 2 g ss Vp (1- (Wpu / WFE1 /), the blocking voltage of the FET, Vp , which is about -1 V, being assumed equal for the FET 44 and for the elements PU 60 and PD 58. Luckily, this tendency of V to the threshold to become more negative when V becomes g P

  more negative, is accompanied by a corresponding increase

  of IpD, because of the increased Idss current of the polarization FET

  connected to the negative supply voltage, PD, 58.

  Considering the finite direct resistance of the chain of

  offset diodes 46, 48 and 50, we note that this increase

  tion of the bias current increases the decay voltage

  lage, VDECALAGE. Since the input threshold voltage is given by V (at the threshold) plus VDECALAGE 'the result

  consists of some cancellation between these two terms.

  In the CDFL circuits, the offset diodes 46, 48 and 50,

  series resistance and polarization levels, determine

  by the size of the PD element (connected to the negative supply voltage) 58, can be carefully chosen to provide a complete first-order cancellation of these terms and thus, at the first order, a zero voltage variation input threshold in the presence of a variation of V (again assuming the uniformity of the short distance FETs, so that the voltage V is the same for P

* the FET 44, the PU element 60 and the PD element 58). Supposed

  the characteristics of the FET correspond to a quadratic law (Ids = K'W (Vgs - Vp) 2, denoting by W the width of a MESFET and by K 'a constant related to the fabrication process of the MESFETs), and assuming for the diodes a model corresponding to a series resistor plus a perfect logarithmic diode (VF = RSIF +. (nkT / q) box (IF / Is), denoting by IF the direct bias current), this cancellation is realized first order by matching the variation of V -Vss at the threshold (ie the g ss

  value of V-V needed to make identical

g ss

  FET 44 and PU 60 elements; see the formula

  above), with the voltage V equal (but opposite) to the

  riation of the offset circuit voltage under the effect of Vp. The total dynamic resistance, RD, for an N diode shift circuit (N = 3 in the preferred embodiment) is RD = N (Rs + {nkT / q) / IF), where n is the factor of perfection of the diode and with kT / q = 0, 02585V

  at T = 300 K. First-order cancellation is obtained when

  that ID R = - (Vg -Vs), denoting by IpD = I the cou-

  PD D 2 g ss Nominal polarization PD of the offset diode, and Vg -Vss = Vp (l - (Wpu / WFET) / 2) the gate voltage of the FET at the threshold. one can realize the equilibrium by choosing the ratio of the dimensions between the FET and the element PU, or by modifying either the polarization current (IpD) which crosses the shift circuit (IDSS of the element PD 58), or the series resistance offset diodes 46, 48 and 50, by a modification of their geometrical configuration (or by the incorporation of a resistor in series with them). We

  note that by placing resistance between the source of the

  PD 58 and VEE, one can modify the variation of IpD as a function of V. Those skilled in the art can establish similar relations p to obtain, by design, the independence of Vth vis-à-vis V. The input current applied to the logic gate

  would be equal to the polarization current of the diode of

  (a typical value of approximately 0.2 mA), if the

  input power source 56 connected to the power supply voltage

  positive attitude was not present. Although this level is not too high, a lower input bias current is desirable for many applications,

  so that one can use the input source 56 con-

  connected to the positive supply voltage to cancel the bias current of the offset diode, so

  to give an input bias current resulting from

  100 microamps for the logic gate.

  Although the design ensures the first-order independence of the door entry threshold voltage

  compared to the variations of the blocking voltage of the D-

  MESFET makes it possible to manufacture compatible circuits

  with ECL signal levels, it would also be desirable to

  table, at least for certain applications, that the threshold voltage is independent of the temperature. The fact that

  the direct voltage drop of a diode, with constant current

  As a result, it decreases in a linear manner as a function of temperature (negative temperature coefficient) at first sight shows the CDFL type shift structures as a marginal choice with regard to temperature stability. However, the mobility of electrons in the GaAs varies inversely with the absolute temperature

  (Jn T 1), so that the resistive ohmic resistor

  implanted in GaAs is proportional to the temperature

  absolute temperature (positive temperature coefficient). By con-

  here again, by carefully designing the

  and carefully choosing its operating point

  It is possible to obtain a cancellation level that is im-

  between the terms related to the junction (coefficient of

  temperature) and those related to resistance (coefficient

  temperature), so as to minimize the coeffi-

  ficient temperature of VDECALAGE. Of course, some of the ECL technologies with which the GaAs components must be compatible, themselves have a significant temperature coefficient. It is obviously impossible to do

  so that the temperature coefficient of a single component

  corresponds to the set of temperature coefficients.

  Signal level re, covering an extended range, of these various logical families. The VAJUSTAGE input 52 of the circuit of FIG. 3 provides the solution to this problem in critical applications. This potential, for which VEE is normally defaulted, varies IpD (the bias current of the level shift circuit), and thus VDECALAGE 'to accurately adjust Vth. For a tension

  ECL threshold (VBB), a simple circuit can be used.

  baked operational amplifier to produce the necessary VAJUSTAGE potential so that GaAs gate thresholds follow the temperature variation of the ECL threshold (VBB). Reaction circuits could be incorporated on the chip to produce this VAJUSTAGE potential from an external VBB input to achieve this threshold tracking. The principle of this tracking is to apply a potential, VBB, equal to the threshold voltage ECL, to an equivalent CDFL gate, having the same input shift circuit structure and the same Wpu / WFET ratio, so that its input voltage is identical to that of the input or inputs of the door or active CDFL doors. The operational amplifier is used to send a signal back to VAJUSTAGE in order to stabilize the output of this

  door to its exit threshold (this counter configuration

  reaction will be obvious to those skilled in the art).

  The use of the form envisaged above, in which a resistor is used between the source of the element PD 58 and VEE, is more convenient to carry out a reaction on the chip, insofar as it is then not necessary. than

  VAJUSTAGE becomes more negative than VEE, which is usually

  the most negative potential available on the chip.

  The design objectives for the CDFL output circuits include the ability to drive a wide range of termination voltage combinations (ATVs) and

  output impedance (RL), with signal levels of

  ECL, allowing characteristically

  logical operations corresponding to the wired OR function (connection of sources), between several GaAs gateways attacking the same node. The most important problem

  here consists in that silicon-bipolar ECL circuits

  are greater than the normal level for high logic input signals, because for VIN> -0.6 or -0.5 V, the bipolar input transistor tends to become saturated , which considerably degrades its blocking time at the suppression of the high state. On the other hand, if a MESFET output circuit is robust enough

  to attack the midpoint of a transmission line

  50 Ohm mission (charged at both ends, so that we actually have RL = 25 ohms), the current of attack of

  output required in the high state (approximately -0.8 V) may exceed

  50 mA, while with high impedance lines (eg 100 ohms to -2VTT), only about 25% of this current (about 12 to 17 mA) is sufficient. Because of this finite output impedance of the gate (about 12.5 ohms), there is a

  tendency to exceed the high exit levels

  combinations with low loads are used.

  current, which unacceptably degrades

ECL circuit trainings.

  Figure 3 shows the output configuration used to solve this problem. The basic output device is a large common drain transistor 54 (the gate width W is typically about 600 micrometers or more), the drain of which is

  connected to a 0.0 V VDD power supply (or posi-

  tive), which is designated VDDO (distinct from VDDL to avoid interaction). The grid attack signal that

  is applied to the common drain FET 54 can go from a va-

  their high almost equal to VDDL up to a low value

  significantly higher than VSS, which is sufficient to block substantially all of the output current in common drain FET 54 at characteristic output levels of -2 V (using Vss = -3.3 V with MESFETs for which V = 1.0 V), which makes it possible to carry out a wired OR function p at the output. The size of the common drain FET 54 allows it to

  provide more than 80 mA (70 mA steady state) (depending on

  V out VDDO, and VDDL); with VDDO = VDDL = VDCH = 0,

  a high output state appears in the form of a resistance

  this is about 12.5 ohms for VDDO = OV. This offers excellent

  your ability to attack an output charge, but if-

  gnifies that with high load impedances, the high output voltage level, VOH, will be greater than the optimum value for ECL circuits (for example, with RL = ohm for MTB = -2V, VOH is approximately equal to

  -0.25 V). We can use the potential of fixing

  driver, VDCH to abruptly limit the positive gate drive voltage applied to the common drain FET 54 (at the start of direct conduction of the Schottky DDCH 62), eliminating this

  problem. This passive diet (which absorbs energy

  gie) VDCH (typically of the order of VDCH = -1.75 V), is selected according to the combination

  particular of the RL and ATV load that is used.

  Although the use of the fixation potential

  higher level VDCH may be necessary to maintain

  the output compatibility with the ECL circuits, this

  is generally not the case for the feeding of fixa-

  VDCL, since the circuits

  Silicon Bipolar ECLs are not sensitive to a

  passing the signal in the negative direction. Optional VDCL power supply can be used

  low level and operating from the beginning of the conduct-

  direct saturation diode by speed DDCL

  61), to allow the optimization of performance, in par-

  especially with high negative MTB values (for example ATV = -3.3 V or -5.2 V), in a manner similar to the potential VLCL TT envisioned previously (Figure 2). As with VLCL, the use of the VDCL power supply will slightly increase the power dissipation on the chip, but the use of the saturation Schottky diode structure by the special type speed previously considered for the DDCL diode 61

(Figure 3) minimizes this effect.

  The capacitor-coupled diode FET logic circuit structure provides charge current efficiencies in digital circuitry using

  D-MESFETs, which are approaching those of

  enrichment. The structure is simple and direct and provides

  an excellent tolerance vis-à-vis the parameters of the dis-

  positive results without significant degradation of

  performance. Although the area required for the offset capacitor (DCAP) increases somewhat the area of a CDFL gate, the penalty at the area level

  is low and the resulting circuit areas, although

  than those of SDFL, are comparable to other FET logic circuits

  performed with D-MESFETs (eg BFL structure).

  The CDFL structure is also suitable for the realization of I / O structures controlled by a threshold, such as circuits

  ECL I / O considered in connection with FIG.

  The performances obtained with CDFL doors correspond to a range of operation of the order of the

  up to 3 GHz, in input, logic and

  that and exit. The I / O circuit of Figure 3 can

  logical delays between entry and exit of

  up to 75 picoseconds, with entire levels

  between an input on a 50 ohm line loaded, and the output circuit driving a 50 ohm line,

  through protective entry and decommissioning circuits

  and by the logic stage. Type D flip-flops to de-

  cleavage on conventional type fronts, made using NOR gates and manufactured by a GaAs integrated circuit fabrication process with a conventional 1 micrometer gate length, have operated with clock of 3 GHz or frequencies of

  3 GHz switching in splitter configurations.

  The CDFL circuit structure has also been used, but with modified feed levels, in association with

  a slightly more special rocking architecture (used

  reading logical FET combinations of serial-parallel type

  and double grid, to obtain configurations of

  complementary doors AND / NON-OR and OR / NAND), in order to obtain

  nier, in a single clock input splitter (not complementary), a nominal maximum tilt frequency of

  4 GHz. Considering the fact that a GaAs divider

  generating fast output signals corresponding to division factors of 2, 4, 8, 16, 32, 64 and 128, in a medium integration circuit, a gate complexity, operating up to a rate clock speed of 3 GHz, dissipates only about 600 mW (excluding the ATV power consumed in the load, which is typically 25 to 40 mW for each output used, depending on ATV and RL), it is clear that these circuits

  embedded in the CDFL type GaAs offer outstanding performance

  with minimum power requirements.

  It goes without saying that many modifications can

  can be made to the device described and represented,

  without departing from the scope of the invention.

Claims (12)

  1. Electric potential shift device   fixed circuit (22) for transmitting a signal current   tative, characterized in that it comprises means of   (12, 14, 16) connected in parallel to   capacitive means (10), and that the combination of   a polarization means (12, 14, 16) and capacitive means (10) are connected in series with current absorbing means (18) so as to establish a defined voltage offset between an input and an output   in a semiconductor integrated circuit.   2. Device according to claim 1, characterized   in that the semiconductor integrated circuit is a positive to GaAs.   3. Device according to claim 1, characterized   in that the biasing means comprise at least one Schottky diode (12, 14, 16) and the capacitive means comprise a reverse biased Schottky diode (10).   having a high capacity per unit area.   4. Device according to claim 1, characterized   in that the capacitive means consist of a high capacitance inverse polarized Schottky diode (10) per unit area, in parallel on a MIM capacitor formed by a Schottky-type metal contact with the diode, and by   a second-level metal electrode connected to the body   thode of the diode, this MIM capacitor being above the Schottky type metal contact but being separated from   this one by a thin insulating layer.   5. Device according to claim 2, characterized   in that the current absorbing means (18)   attempt in a D-MESFET type transistor.   6.Dispositif according to claim 5, characterized in that the current absorbing means consist of a D-MESFET transistor (18) with a resistor connected to its source driver.   7. Fixed voltage device characterized in that   it comprises polarization means (12, 14, 16)   connected in parallel with capacitive means (10), and   what the parallel combination of polarization means   (12, 14, 16) and capacitive means (10) is connected   in series with current absorbing means (18).   8. Device according to claim 1, characterized   in that the polarization means (46, 48, 50) and   the capacitive means are connected to fixing means   level (44, 42) and saturation resistance   (381, to protect logic circuits against excur-   high input voltage levels.   Protective device for protecting an input of a semiconductor device, characterized in that it comprises level fixing means (40,   42) connected to a saturation resistor (38), for   to manage logic circuits against voltage excursions high input.   o Device for limiting a tour of   negative voltage characterized in that it comprises a   saturation diode (34) connected to a current source and switching means (24, 20, 28) for the purpose of reducing a   negative potential excursion when the means of communication   mutation are in a conductive mode.   11.o Device for limiting a positive voltage excursion, characterized in that it comprises a Schottky diode (30) connected to a current source and to switching means (24 20, 28), for the purpose of reduce a positive potential excursion when the switching means are in a non-conductive mode.   Apparatus for limiting an output voltage swing of a GaAs device, characterized in that it comprises a Schottky diode (62) connected to a current source, switching means (44) and switching means. (54), in order to limit the level positive of the output voltage.   Device for limiting an output voltage excursion of a GaAs device, characterized in that it comprises a saturation diode (61) connected to a current source, switching means (44) and output drive means (54) for the purpose of limiting the   negative level of the output voltage.