DE3537404A1 - CAPACITY DIODE FET LOGIC CIRCUIT FOR GAAS D-MESFET INTEGRATED CIRCUITS - Google Patents

Description

GIGABIT LOGIC, INC., NEWBURY PARK, CALIF. / UNITED STATES

Capacitance diode FET logic circuit for GaAs D-MESFET integrated circuits

Historically, the most agonizing problem has been in the design of MESFET GaAs integrated circuits of the depletion type in realizing the level switching function between the positive drain voltage to the Operation of these N-channel D-MESFETs was required and the negative gate voltages that were necessary to turn off other D-MESFETs. In contrast, will with a simple, directly coupled FET logic (DCFL), the FET gate inputs of the enhancement type are included directly connected to the drain outputs. Thus, the settling gate output current for the control is one typical capacitive load during the increase (in sourcing) essentially equal to the increasing active load current,

which is the same size as the direct current supply current, and which can be several times that when lowering (in sinking). In general, none of the D-MESFET circuits comes close to the published direct-coupled FET logic circuits in terms of efficiency (as defined by the ratio of load current control capability to supply current), and even less in terms of simplicity. On the other hand, the enhancement-type field effect transistors made from GaAs (E-MESFET, E-JFET, and E-HEMT) are fraught with serious manufacturing problems, primarily affecting their limited gate swing (/ \ V _T is approximately 500 mV in E-MESFET DCFL circuits) and the resulting control of the gate threshold voltage ( ff V should be less than or equal to V _T / 20 in order to achieve good exploitation and good performance in LSI up to VLSI circuits, which is approximately 25 mV for the E-MESFET). The D-MESFET technology uses larger logic voltage swings (typically ^ V corresponds to approximately 1V to 2V in D-MESFET logic circuits) with regard to the required uniformity, where ^ V is approximately 50 to 100 mV over a chip, a value which can be easily realized in the manufacture with the current manufacturing technology for GaAs integrated circuits.

The ease of manufacture and higher switching speeds of a D-MESFET GaAs IC make these circuits very good The implementation of the voltage-0 switching function has made most of the published D-MESFET circuits make serious compromises in operational

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behavior and / or performance efficiency. In the original Hewlett-Packard (HP) buffered FET logic circuit (BFL, see R. L. VanTuyl, C. A. Liechti, R. E. Lee and E. Gowen, IEEE JSSC, SC-I2, p 485, 1977), the switchover took place in a separate SOURCE follower output stage, resulting in a maximum Sinking current drive of only about 60% of the supply current resulted in some speed losses as a result of delays in the output stage. In later work from Hewlett-Packard, the SOURCE follower in favor of a direct one for slightly loaded gate electrodes 3-diode chain for pulling down is omitted (about half the width of the active pull-in load). These "unbuffered" FET logic circuit (BLFL, see Barna,

A. and CA. Liechti, "Optimization of GaAs MESFET Logic Gates with Subnanosecond Propagation Delays", IEEE Journal of Solid-State Circuits, SC-14, August 1979) provided improved delays for low output branches, but still gave a current efficiency of about 50% ( the output could rise or fall by about 50% of the supply current), as well as an even lower degree of efficiency, since as with the buffered FET logic circuit (BFL) this large current to -V ^ _1. , and not to V "" (ground at BFL ) goes. This "unbuffered" FET logic circuit also creates another problem of current differential. The available load current is the difference between a large pull-in current and a large pull-down current, so that if the ratio between the currents changes (for example as a result of statistical parameter changes

or "backgating") the available load current drive is severely impaired. This Problem is even more serious in an FET Schottky diode circuit (SDFL, see U.S. Patent 4,300,064 and Reference 3, R.C. Eden, B.M. Welch, R. Zucca and S.I. Long, IEEE Tran. Electron Devices, ED-26, No. 4, pp. 299-317 (1979) or SC-14, No. 2, pp. 221-239 (1979), where as a result of Using a diode logic circuit the pull-down load is heavy and, in fact, changeable, dependent from the output branch and the logic state of other gate inputs on the loaded gates. From the point of view the current efficiency is a capacitance-coupled FET logic circuit (CCFL, see A.W. Livingstone and P.J.T. Mellor, "Capacitor Coupling of GaAs Depletion Mode FET's" 1980 GaAs IC Symposiom Abstracts, Paper No. 10) excellent (about the same as DCFL) and allows operation with single supply, however, CCFL gates cannot be up to direct current (de) work, which is usually unacceptable in logic applications. Furthermore, the published CCFL circuits in the reverse direction operated Schottky diodes, which are on the FET η -channel layer for the coupling capacitors are upset. With the normal reverse bias of these varactor diodes, this n ~ layer was pinched off, so that the capacitance structure was very complicated and related the use of space showed a low level of efficiency. A similar mode of operation, but up to direct current was applicable, was achieved by adding a feedforward capacitor to the BFL gate arrangement (FF-BFL, see M.R. Namordi and W.A. White, IEEE Electron Device Letters,

V.EDL-3, No. 9, September 1982, pp. 264-267), but with a noticeable loss of power efficiency and complexity Structure as a result of the SOURCE follower output stage.

The invention relates to the use of a logic gate circuit coupled to a capacitance diode for design of GaAs D-MESFET logic circuits, which are directly coupled (de) to operate at very high speeds and typically allow 90 to 97% power efficiency (CDFL gates can be used in SOURCE give approximately 90 to 97% of the supply current and reduce it up to a multiple of this.) Also required this gate circuit considered according to the invention not the complication of a SOURCE follower output stage on each gate. The one in question CDFL arrangement is based on the knowledge that in FET logic the load currents are essentially capacitive. This means that the best voltage switching element would be a tiny battery that is on the chip between the D-MESFET drain electrodes at the FET logic node and the gate output is integrated. With pure capacitive Loads, no net DC power is required, and indeed would be, from such a battery the battery is charged and not discharged when the gates of the MESFETs connected to the output occasionally become conductive in the forward direction. There are no such Battery assemblies in integrated circuits are currently available, a suitable replacement is the minimal power required or minimal complications caused, desired.

The invention is therefore based on the object of providing a fixed-potential switching circuit for integrated GaAs To create circuitry that increases load current driver efficiency without noticeable signal delay and which is of an acceptable size, i.e. the gate density of the integrated circuits not reduced inadmissibly. Another object of the invention is to provide a number of specific Create circuit techniques for D-MESFET logic circuits, including Schottky diode clamping with "high" deduction and saturation diode clamping with "low" deduction, which increases the logic delay times or can further improve switching speeds. Another object of the invention is to provide input circuits indicate the saturation resistance (SATR) Schottky diode clamping techniques in conjunction with a CDFL switch, use both one Protection against burnout in the event of gross logic input signal overload and strict control of the input threshold voltage enable (even if the MESFET necking voltage changes as a result of process changes changed), so that a signal compatibility with common bipolar, emitter-coupled logic circuits (ECL) based on silicon.

Finally, the invention is based on the object of specifying output circuits which have a "high" clamping by means of a Schottky diode and a "low" clamping by means of a saturation diode at the gate input of a SOURCE follower output device which allows the circuit to be phantom-ORed as well as a controlled ECL

Output signal compatibility over a wide range of load resistance and output voltage combinations .

According to the invention, this object is achieved by a fixed-potential switching device solved, which is characterized by a biasing device which is parallel to a capacitance arrangement, the parallel arrangement the biasing device and the capacitance arrangement are in series to form a sink arrangement, a controlled voltage switch between an input and an output in an integrated semiconductor switch to achieve.

The invention will then be explained in more detail with reference to the drawings. Show it:

Fig. 1 a CDFL voltage switching switch

tion,
20th

Fig. 2 shows a typical CDFL NOR gate

device with a CDFL level switching device on the output side, and

Fig. 3 an ECL-compatible CDFL input /

Output circuit for a logic inverter.

Referring now to Figure 1, the varactor diode FET logic circuit (CDFL) provides the switching device according to Fig. 1 as sufficiently close

A substitute for the ideal battery mentioned earlier in the Summary of the Invention. The circuit consists of a capacitor (DCAP) 10, which by an essentially constant voltage, V _otJX " _m ,

OnXr J,

is kept charged by means of a small current flowing through a chain of three small Schottky diodes 12, 14 and 16. The small bias current is supplied by a very small pull-down current sink PD 18, which is connected to a negative voltage supply, V "" (V ₁ -, - should be about 1 volt or greater, more negative than the most negative output-side logic swing if D-MESFETs with V = -1.0V constriction voltage can be used for PD 18). Furthermore, I, is approximately equal to I,.

Correct operation of the switching device according to FIG. 1 is obtained when the capacitance of the switching capacitor DCAP 10 is much larger than the load capacitance 20 (typically 3x to 10x larger than the load capacitance C _t ). Under these circumstances, indeed

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mainly the total input-side alternating current into the load and the voltage gain of the switching device ^{for the high-frequency alternating voltage Λ ν} τ / Δ ^{ν ΐΝ = C} DCAP ^{/ (C} L ^{+ 0} DCAP * ^{approaches 1 (0 '75 to>} °' ⁹⁾ 'during other capacitance arrangements, such as MIM (metal-insulator-metal) capacitors with hoh ^ m 6 could be used for DCAP, a reverse-biased Schottky diode arrangement with a particularly high C / A (capacitance divided by Flär .he) This arrangement is used

1 7 on a relatively heavily endowed (? 2x10 / cm ² )

Implant made of sufficient thickness to ensure normal, reverse-acting Bias voltage no constriction occurs (the switching voltage V is approximately 2.3 V for a switching device working with three diodes). The DCAP capacity can also be used without additional effort in chip area can be increased by adding the diode capacitance to an MIM capacitance of an additional metal layer electrode a second layer is connected in parallel, which is connected to the diode cathode and to which Upper side of the Schottky anode metal lies, but separated from it by a thin dielectric layer is. This basic switching device 22 can be used anywhere in the circuits if a Level switching is required, for example in Input / output circuits (I / O), with gate inputs, Gate outputs, etc .. A simple CDCL NOR gate arrangement with three inputs, which uses a CDFL output level switching device, is shown in FIG. It is also possible to use the CDFL switching devices in an equivalent manner at each gate input to be arranged so that the line connection capacities do not have to be operated via DCAP 29, so that the Area of DCAP 29 can be made smaller, but this requires more switching devices than typically there is a multiple higher number of gate inputs than gate outputs. The three drain-dotted n (parallel connected) D-MESFETs 24, 26 and 28 which are used to achieve the NOR function in FIG demonstrate CDFL gating training. In general, different series-parallel-

Combinations of D-MESFETs can be used to achieve different logic functions in capacitance-diode-coupled FET logic (CDFL), as well as in other types of FET logic- The use of dual-gate FETs or series and parallel combinations of FETs for achieving different logic functions in an FET logic gate circuit are known to the person skilled in the art, as are the use of other types of load devices, such as, for example, saturation resistors, gate-free FETs, resistors or resistance combinations with FETs, such as the pull-in load 33 and / or pull-down load 35 (or 18 in Fig. 1 or 56, 58, or 60 in Fig. 3). This circuit is shown with the usual power supply potentials for ECL-compatible operation (V _DD , = ground, V_ "= -5.2 V as standard ECL supplies, too

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to which a power supply V _ = -3.3 V was added). For more common GaAs IC operation, ν _ςς = ground, V__ = -1.9 V (or more negative) and V _DD _ = +3.3 V (or more positive). With the special FET dimensions shown, this circuit requires a maximum supply current of (^ noo / ^ ^x 16.5 micrometers (W = gate width), while the circuit requires up to (I _Sg / W) χ (16.5-1.5 Micrometers = 15 micrometers) (SOURCE), so that the current efficiency (sourcing) is equal to 15 / 16.5 = 91%. The current efficiency when lowering can be several hundred percent (depending on the maximum input voltage), even starting from one single entrance.

The CDFL NOR gate arrangement of FIG. 2 illustrates also another one developed for GaAs circuits

Technique for maintaining operation with high Speed over a wide range of supply voltages (V-Tvr-V ,, ^ = 3.3 to 7 volts) if desired.

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In conventional FET logic circuits, the logic high lift is limited by the positive supply voltage (V _nT -V) by means of the "soft-limiting" effect of an active pull-up load, PU, which results from drain saturation. While V _., ^ _T -V__ increases, the positive logic swing increases until the point in time at which the Schottky gates of the loaded MESFETs change to a hard conduction state. This last state brings the MESFETs into an extremely poor ΐγ operating range (very high gate capacitance C with poor counteractive tail g), with deteriorating performance in addition to that caused by the excessive logic voltage swing itself (the switching transition time of a capacitive load C-, at a constant load current I _T , with the switching taking place via a logic lift voltage ^ V _T , is approximately ^ t = C ₁ ^ V ₁ - / I _T ) The optional use of a Schottky switching diode 30, DLCH, for logic high clamping with a clamping potential V _Tr , “ provides a hard limitation of the positive logic swing, regardless of ν _πΓ . _τ -ν _οο , whereby the

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mentioned deterioration of the operating behavior with changing supply voltage (ie increase of ^ V with increasing V _._ _T ) is prevented. The V _T _ potential

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can be obtained from a passive feed, for example from a Zener diode alone, since it only lowers the _{current to V cc.} An on-chip current sink voltage regulator supply output may be provided to provide a nominal V clamping potential.

Of slightly less concern, but with some means of improving operation, is the use of an optional V _T input 32 to further control the logic strokes by clamping the logic low with the optional diode 34. This has the effect of not only a delay is reduced by reducing ^ V, but also the MESFETs outside the very low V range (at high V)

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be held in which f ^ r is bad. These Clamping, however, requires an active power source (power sourcing) and thus increases the "gate radiation". This could make the use of V-, inconvenient

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make, if this were simply used, since if all three input-side MESFETs 24, 26 and 28 in the gate according to FIG. 2 were switched to V = +0.8 V, the resulting total drain current with a hard clamping is ten times the active load pick-up current I would achieve _. This operating condition is avoided by the use of a special speed saturation Schottky diode arrangement 34 for DLCL, which performs a controlled current limitation when the current in the forward direction exceeds a specified level. This prevents an excessively large V _T _, _T current,

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when many parallel logic FETs are turned "ON" simultaneously (e.g., FETs 24, 26, and 28 in Fig. 2), however, still ensures optimal logic operation by setting the logic low to its correct level Value is returned when some of the gate inputs are turned off. The speed saturation diode which is used for DLCL 34 (and also for DDCL 61 in Fig. 3) is a planar Schottky

Diode arrangement which uses the same η implant (using the same technology according to reference 3) that is used for the switching Schottky clamping diodes (for example 30 according to FIG. 2 and 40, 42 or 62 according to FIG. 3). However, these saturation diodes are designed with a carefully monitored periphery of the anode of the diode (Schottky contact) to control the maximum current in the forward direction, and they are also designed so that the current in the metal contacts at this saturation current in the forward direction does not cross the metal migration limit for the intermediate metal used (I corresponds approximately to 1 χ 10 A / cm ² for gold). The saturation current in the forward direction of the speed saturation diode 34 or 61 is essentially proportional to the anode periphery of the diode (circumference of the Schottky contact which effectively touches the η implant), the constant of proportionality being approximately 1 mA of the saturation current in the forward direction per 1 micrometer of the Anode circumference for the typical, approximately 450 ohm / pn implants that are used for GaAs IC Schottky switching diodes. In some applications, the modest improvements in speed by the V ₁ warrant. _, _T application can be achieved, not the additional complication, according to which an additional potential input (power sourcing) is required and an additional, albeit relatively low chip emission is caused, so that DLCL 34 can be omitted or, if provided, a standard connection from V _T _, _T to V " _o can be used.

A basic gate structure, such as the CDFL NOR gate according to FIG. 2, can be used to with to implement logic in the circuits with good efficiency, but it generally becomes unusable its interface applications related to chip in and chip out. GaAs digital IC outputs will be often required to bring transmission line impedances to standard ECL while the inputs must be compatible with ECL signals and also be resistant to damage due to overdrive with strong signals or static discharge and the like. Fig. 3 shows one Inverter structure using both CDFL input and output assemblies. The inverter circuit shown 36 is unusual in that both the chip input and output circuits are on the same Level (on most chips these circuits are separated by a number of logic levels), however, the I / O switching principles are the same.

The signal inputs are controlled by a bidirectional current limiter, SATR (saturation resistor or gateloses D-MESFET) 38 and clamping diodes DICH (input-side clamping diode high level) 4 0 and DICL (input-side Clamp Diode Low) 42 in combination which allows AC signal levels up to approximately 4 0 volts, measured from peak value to peak value (+ 4OdBm) in the steady state without adverse effects or failure of proper circuit operation. The current limiter 38 has a low resistance of 30 to 40 ohms for the

(normal) low applied voltages, but with applied voltages above approximately takes place + 1V the arrangement as a current limiter with I of

sat

approximately jMOmA. (In most D-MESFET GaAs IC processes, the current limiter can be fabricated in the same way as a D-MESFET, omitting the Schottky gate electrode, which is normally located above the n ~ channel between the n ⁺ -implanted SOURCE- This "gateless FET" bidirectional current limiter has been described in the GaAs IC literature. For simple input protection, standard clamping voltages of V _{T. D} = V _r . _r . _T = 0.0V (ground) and

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V = V ₀₀ = -3.3V what the internal

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Signal voltages are limited to a safe (but overdriven) voltage range of +1.2 to -4.5V. This input arrangement can also expediently be used to produce internal square wave signal voltages from uncontrolled sine wave signals. This squaring is usually _{done by connecting V T} _. " ~ V_" _T = -1.3V (the ICL signal threshold).

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men, typically a blocking capacitor in the input signal line is used to each DC component to remove, whereupon a 3V to 20V _ (+ 13dBm

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up to + 3OdBm) sine wave input signal is supplied, to produce an inner square wave signal of approximately 2V _ (-0.3V to -2.3V). With normal input signal levels from -0.8V to 1.8V, the current limiter 38 actually has no effect on the operating behavior as a result of its low resistance value (approximately a 5ps delay is typical.

The main problem with input is maintaining the proper -1, SV input threshold voltage V ,, for operation compatible with ECL signals over the range of D-MESFET necking voltages normally encountered in the manufacture of G ^ As integrated circuits (above V = -1.0 + 0.2V). The key to controlling threshold voltage is to take advantage of the fact that near-range changes in V (changes in V measured within areas less than about 1 mm apart) as opposed to changes from one wafer to another that are the largest (with slow gradations for platelets that are closest in size). Since the width (W _p ") of the pull-in FET 60 and the switching FET 44 are uneven, the gate voltage V -V at the threshold is not zero / V -V

g ss 1 / 2- "

is approximately equal to V (1 - (Wp "/ W"" _T ). _ /, where the FET constriction voltage V is approximately -1V and is the same for the FET 44, the FET PU 60 (pullup) and the FET PD Fortunately, this tendency for V at threshold to become more negative as V becomes increasingly negative is _{accompanied by a corresponding increase in I pD} due to the increased I, of the pull-down FET PD 58. Regarding on the finite resistance of the switching diode chain 46, 48 and 50 in the forward direction, this increase in bias current will increase the switching voltage V. Since the input threshold voltage as V (at the threshold

g + V "" _TT , _m ) is given, the result will be a deletion

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occur to a certain extent between these two quantities. In the CDFL circuits, the switching diodes 46, 48 and 50 as well as the series resistor and the Bias levels, as determined by the size of the FET PD (pulldown) 58, are carefully measured in order to result in a complete deletion of these expressions with regard to the fundamental oscillation and thus a zero change in the input threshold voltage with a variable V with respect to the fundamental (again assuming close range FET uniformity so that V is for FET 44, FET PU and the FET PD 58 are the same size). This deletion with regard to the fundamental oscillation is achieved on the basis of

laying of the square (I, = K ¹ W (V -V)) FET-

Q. s * 3 "* ^ P

Characteristic curve (where W is the MESFET width and K ^{1 is} a process constant for the MESFETs) and a series resistance plus an ideal logarithmic diode model for the diodes (V "= R _O I" + (nkT / q) log (1 .., / I ₀ ), where I represents the forward bias current by taking the change in VV at the threshold

y SS

(i.e. the value of V -V required to achieve the

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Currents from FET 44 and FET PU 60 identical - see above formula - to be made) with V, same size (but opposite

P.
set against) is made to change the switching voltage with V. The total dynamic resistance R for a switching device with N-diodes (N = 3 in the preferred embodiment) becomes R ^ = N (R + (nkT / q) / T) , where η is the ideality factor of the diode and kT / q = 0 , 02585V at T = 300 ⁰ K. The deletion with respect to the fundamental occurs when I _13n R _n = · * ■ (VV), where I = I _f denotes the diode

IrU U ^ y SS JrU X

Represents bias current for nominal switching

and VV ₃₅ = V ( ¹ - ( ^w _PU / ^w _FET ) f) is the FET gate threshold voltage. The equilibrium can be achieved by selecting the FET according to the PU size ratio, or by either changing the bias current (Ip _n ) through the switching device (I _n C _{0 of} the FET PD 58)

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or the series resistance of switching diodes 46, 48 and 50 is changed by changing their geometry (or placing a resistor in series with them). It should be noted that by placing a resistor between SOURCE of FET PD 58 and V "" the change of I with V can be influenced. Similar relationships for establishing an arrangement in which V _m "of

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V is independent in this modified circuit can be derived by those skilled in the art.

The input current to the logic gate would be the same like the bias current of the switching diode (approximately typically 0.2 mA), if the input-side Starting current source 56 would not be provided.

While this level is not too high, for many applications a smaller input bias current is required is desirable so that the input-side pull-in current source 56 can be used to generate the bias current to reverse the switching diode to at least less than 100 mA net input bias current for to deliver the logical gate.

While a draft that has an independence of the fundamental of the gate input threshold voltage versus changes in the D-MESFET throat voltage ensures that the manufacturability of the circuits is

tible with the possible ECL signal levels, a temperature-independent threshold voltage would also be desirable, at least for some applications. The fact that the forward voltage drop at constant current for a diode drops essentially linearly with temperature (negative temperature coefficient) makes the CDFL switching arrangements at first glance only marginally suitable for temperature stability. However, with GaAs the electron mobility changes inversely proportional to the absolute temperature (μ o6T) so that the ohmic resistance of implanted GaAs resistors is proportional to the absolute temperature (positive temperature coefficient). Thus, again, with careful device and operating point design, it is possible to achieve a substantial amount of cancellation between the transition member (-TC) and the resistive member (+ TC) as small as _{the temperature coefficient of V SHIFrT} to make possible. Of course, some of the ECL technologies on which the GaAs devices are to be placed have a significant temperature coefficient of their own. It is clearly impossible to tune together all of the temperature coefficients associated with the wide range of signal levels of these various families of logic. The working procedure for this problem in critical applications is determined by the V-

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Input 52 for the circuit of FIG. 3 is supplied. This potential, which is normally set to V "" standard

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is set, changes I _pn (the switching bias current), and thus V, to set V, precisely. If

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Lower ECL threshold voltage (V__,) can be a simple

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Operational amplifier circuit can be used to generate the V potential that

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is necessary so that the threshold values of the GaAs gate correspond to the temperature changes of the ECL threshold (V_ _n )

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follow. Feedback circuitry for generating this V “ _RTM potential from an external V input could be provided on the chip to perform this threshold following operation. The principle of this subsequent process is to input a potential V, which is the same as the ECL threshold voltage, into an equivalent CDFL gate which has the same structure as the switching device on the input side and the same ratio of W_. _TT to W _n ,,., So that their input

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output voltage is identical to the active CDFL gate input or inputs. The operational amplifier is used to convert a signal to V _mi -, _ .. in such

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Way so that the output of this gate is stabilized at its output threshold (this negative feedback arrangement would be obvious to a person skilled in the art). The use of the arrangement explained above, in which a resistor is used between SOURCE of FET PD 58 and V, is more favorable for on-chip feedback because it is then not necessary _{to make V TTJTM more} negative than V "", the usually represents the most negative potential available on the chip.

The design goals for the CDFL output circuits include the ability to handle a wide range of output impedance (R_) - terminal voltage (V _mm ) - combined

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functions to control ECL-compatible signal levels that

typically maintain logic operations of phantom OR circuits (SOURCE doping) between multiple GaAs gates driving the same node. The greatest difficulty lies in the fact that silicon-based bipolar EGL circuits are sensitive to overdriving with an input-side logic "high", since for V Λ -0.6 or -0.5V the input-side bipolar transistor tends to switch to the To go to saturation state, which noticeably worsens its shutdown time when the "high" is removed. On the other hand, if a MESFET output circuit is sufficiently robust to control the bisection point of a 50 ohm transmission line (which is terminated at both ends, so that effectively R_ = 25 ohms), the required control current for an output high (approximately -0.8V ) Exceed 50 mA, while lines with high impedance (for example 100 Ohm to -2V _T ) only require about 25% of this current (approximately 12 to 17 mA). Because of the finite output impedance of the gate (approximately 12.5 ohms), there is a tendency to overdrive the high output level if a small current-carrying load combination is used, which can unduly impair the performance of the ECL circuit.

The output circuit used to solve this problem is shown in FIG. The basic exit arrangement is a large SOURCE follower 54 (where the gate width W is typically about 600 microns or equals more), the drain of which is connected to a 0.0V (or positive) V voltage source, where

separated from V is arranged to cause interference

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To prevent scattering. The gating to the SOURCE follower 54 can vary from a high value of about V " _DDT to a low value slightly above V, which is sufficient to essentially the

block the entire output current in the SOURCE follower 54 at typical -2V output levels (using V = -3.3V with V = 1.0V MESFETs), indicating an output operation permitted with phantom - OR link. 10

The size of the SOURCE follower 54 allows it (depending on V, V _DD0 and V _DDL ) to operate over 80 mA (70 mA continuously); with ν __ ^ = V ₁ ^ _x = V ^ -, ^ = 0 appears

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an output high as an approximately 12.5 ohm resistance for V = OV. This enables excellent control of the output load, but means that at high impedance loads the high-voltage level V _{0 on} the output side becomes higher than the optimum for ECL (if, for example, R = 100 Ohm for V ₁ -, = -2V, then V corresponds approximately -0.25 V). The high-clamping control potential V ~ _n " can be used to increase the

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positive gate control (via the beginning of the forward conduction of the Schottky diode DDCH 62) to the SOURCE follower 54, thereby eliminating this problem. This passive (power sink) V supply (typically in the order of magnitude of V ₁ ^ ₀ = -1.75V) is used for the respective

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Load R _T and V _m combination selected.

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While applying an upper clamping potential V ^ _, "to maintain ECL output compatibility

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may be required, this is generally not the case for the supply of a lower clamping potential V ₁ ^ ₁ .

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because silicon-based bipolar ECL circuits are not sensitive to negative signal overload. The optional provision of V _DCL (low-clamping control), which becomes effective via the start of the conduction of the saturation diode DDCL 61 in the forward direction, can be provided to optimize the operating behavior, especially with large negative V values (e.g. V = -3.3V or -5.2V), in a similar manner to the V _T _ potential explained earlier (Fig. 2). As is the case for V _LCL , the use of a V _n " _r injection increases the radiation of chip power slightly, however, by using the special velocity saturation Schottky barrier explained earlier in connection with DDCL 61 (FIG. 3) Diode arrangement kept this effect as small as possible.

The use of a capacitance diode FET logic circuit achieves load current efficiencies in D-MESFET digital circuits approaching those of the enhancement type circuits. The execution is simple and straightforward and allows excellent parameter tolerances the arrangement without significant impairment of the efficiency or the operating behavior, namely enlarged the required area of the switching capacitor (DCAP) is somewhat the area of the CDFL gate, however this disadvantage in terms of area is small and the resulting circuit areas are higher than with SDFL, but comparable to other FET logic circuits that

are provided with D-MESFETs (e.g. BFL). The CDFL arrangement is also suitable for installing Threshold controlled input / output arrangements such as those described in connection with FIG ECL input / output circuitry.

The mode of operation that can be achieved with CDFL gates is operation with direct current up to 3GHz in input, logic and output circuits. When fully clamped, the input / output circuit according to FIG. 3 can result in input / output logic delays starting from a closed 50 ohm input line via the input-side protection and switching circuit and via the logic stage and the output-side driver for a 50 Ohm line, which are as little as 75 picoseconds. Known edge-controlled D-flip-flop circuits implemented with a NOR gate, which were produced in a standard process for GaAs-integrated circuits with a gate length of 1 micrometer, had clock frequencies of 3 Hz or toggle frequencies of 3 Hz in divider circuits. The CDFL circuit arrangement was also used in conjunction with a somewhat more unusual flip-flop structure, albeit with modified supply levels (using double gates and series-parallel-logic-FET combinations in order to achieve complementary AND / NOR and OR / NAND gate circuits) to achieve a nominal 4GHz maximum sweep frequency in a single (non-complementary) clock input divider. Considering that a GaAs divider in an MSI circuit with 100 gates '-2 , ' - 4, τ16, τ32, t64 and r128 provides high speed outputs,

and works with a clock frequency of up to 3GHz, only emits about 60OmW (excluding the power of the load V, for whichever output or outputs are used - typically up to 40mW each, depending on V _mm and R _T ), so it is obvious ,

11 J-i

that these CDFL GaAs integrated circuits perform superbly with minimal power requirements exhibit.

Further modifications of the invention are possible within the scope of the appended claims and are encompassed by this.

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Claims (13)

HOFFMANN "·" EITLE & PARTNER 35 37 AO A PATENT AND LAWYERS PATENTANWÄLTE DIPL.-INQ. W. EITLE DR, RER. NAT. K. HOFFMANN DIPL.-ΙΝΘ. W. LEHN DIPL.-ING. K. FÜCHSLE ■ DR. RER. NAT. B. HANSEN · DR. RER. NAT. HA. BRAUNS DIPL.-INQ. K. GORQ DIPL.-ΙΝΘ. K. KOHLMANN - LAWYER A. NETTE 42 810 / wa GIGABIT LOGIC, INC., NEWBURY PARK, CALIF. / UNITED STATES Capacitance diode FET logic circuit for GaAs D-MESFET integrated circuits PATENT CLAIMS ίΙ / Electrical fixed potential switching device for Passage of an alternating signal current, characterized by a biasing device (12, 14, 16), which is parallel to a capacitance arrangement (10), the parallel arrangement of the The biasing device and the capacitance arrangement are in series with a sink arrangement (18) in order to achieve a controlled voltage switching between an input and an output in an integrated semiconductor circuit.
10 ARABELLA STREET 4. D-8OOO MONKS 81. TELEPHONE (Ό893 911087 · TELEX 5-ί? 9ϋ19 (.FATHE} · TELECOPIER oilO356 2. Device according to claim 1, characterized in that the integrated semiconductor circuit is a GaAs device. 3. Apparatus according to claim 1, characterized in that the pretensioning device (12, 14, 16) has at least one Schottky diode and that the capacitance arrangement has a high capacitance per unit area of the Schottky diode operated in the reverse direction. 4. Apparatus according to claim 1, characterized in that the capacitance arrangement is a comprises high capacitance per unit area of the reverse-biased Schottky diode running in parallel with a MIM (metal-insulator-metal) capacitor arrangement, which is through a Schottky metal contact with the diode and a second level metal electrode connected to the cathode of the diode is formed, wherein the MIM capacitor arrangement is above the Schottky metal contact but from separated from it by a thin layer of insulation. 5. Apparatus according to claim 2, characterized in that g e k e η η, that the sink arrangement is a D-MESFET. 6. The device according to claim 5, characterized in that the sink arrangement a D-MESFET whose SOURCE lead is connected to a resistor. 7. Fixed potential device, labeled by a biasing device (12, 14, 16), which runs parallel to a capacitance arrangement (10) with the parallel combination of the biasing device and the capacitance arrangement in series with a sink arrangement (18). 8. The device according to claim 1, characterized in that the pretensioning device and the capacitance arrangement having a clamping arrangement (40, 42) and a saturation resistor arrangement (38) are connected to protect the logic circuits from high input voltage oscillations. 9. Protection device to protect a semiconductor input , characterized by a clamping arrangement (40, 42) connected to a saturation resistor arrangement (38) to provide logic circuits protect against high input voltage oscillations (strokes). 10. Limiting device for limiting a negative voltage oscillation, marked by a saturation diode connected to a power source and a switching device for reducing a negative oscillation amplitude when the switching device is in a conductive state is located. 11. Limiting device for limiting a positive voltage oscillation, marked -A- by a Schottky diode connected to a power source and a switching device for reducing a positive oscillation amplitude when the switching device is in a non-conductive State. 12. GaAs limiting device for limiting an output voltage oscillation, characterized by a Schottky diode connected to a power source, a switching device and a driver output arrangement for limiting the positive output voltage level. 13. GaAs limiting device for limiting a Output voltage oscillation, characterized by a saturation diode, which is connected to a Power source is connected, a switching device and a driver output device for limiting the negative output voltage level.