GB2166312A - Capacitor diode level shift circuit - Google Patents

Abstract

A voltage level shifter 22 includes a revise-biassed Schottky diode capacitance 10 biassed by three small Schottky diodes 12, 14, 16. The bias current is provided by a FET 18 connected to a negative supply VEE. Manufacturability is attained by making the circuits tolerant to variations in MESFET pinchoff voltage and by reducing current differencing. High performance at low power is achieved by minimizing the current wasted in level shifting and by carefully controlling the internal logic voltage swings to maintain MESFET operation in high ET regions. Typical gate operating frequencies are in the dc to 3GHz range with a Lg = 1 micro meter, Vp = -1.0V GaAs D-MESFET process. <IMAGE>

Description

SPECIFICATION Capacitor diode FET logic circuit approach for GaAs D-MESFET IC'S Historically, the most vexing problem in depletionmode MESFET GaAs integrated circuit design has been in achieving the level shifting function required between the positive drain voltage necessary for operation of these N-channel D-MESFETs and the negative gate voltages required to turn off other D-MESFETS. In contrast, in simple direct-coupled FET logic (DCFL), the enhancement-mode FET gate inputs are connected directly to the drain outputs.Hence the transient gate output current available to drive a typically capacitive load is, in sourcing, essentially equal to the pullup active load current which equals the dc supply current, and in sinking, it may be several times this.In general, none of the D-MESFET circuit approaches published approach DCFL in efficiency (as defined by the ratio of load current drive capability to the supply current), let alone in simplicity. On the other hand, the enhancement-mode FETs available in GaAs (E-MESFET, E-JFET and E-HEMT) are troubled with serious problems in manufacturability, principally centered around their limited gate swings (AV, is approximately equal to 500mV in E MESFET DCFL circuits) and the attendant gate threshold voltage control this necessitates ((rVp should be less than or equal to V,/20 for good yield and performance in LSI to VLSI circuits, which would be approximately equal to 25mV in E-MES FET).The D-MESFET technology uses larger logic voltage swings (typically AV, equals approximately 1V to 2V in D-MESFET logic approximately 50 to 100 mV over a chip, a value quite easily realized inproduction with current GaAs IC manufacturing technology.

While the ready manufacturability and higher speeds of D-MESFET GaAs ICs make them very attractive, realization of the voltage shifter function in most of the published D-MESFET circuit approaches has led to serious compromises in performance and/or power efficiency. In the original Hewlett-Packard (HP) buffered-FET logic approach (BFL, SEE R. L. VanTuyl, C. A. Liechti, R. E. Lee, and E. Gowen, IEEE JSSC, SC-12, pp.485, 1977), shifting was done in a separate source-follower output stage, which gave rise to a maximum sinking current drive of only about 60% of the supply current, and suffered some speed loss due to the output stage delay. In later HP work, in lightlyloaded gates, the source follower was deleted in favor of a direct 3-diode chain to a pulldown (about half the width of the pullup active load).

This "bufferless" FET logic (BLFL, see Barna, A, and C. A. Liechti, "Optimization of GaAs MESFET Logic Gates with Subnanosecond Propagation Delays," IEEE Journal of Solid-State Circuits, SC-14, August 1979) gave improved delays at low fanouts, but still gave only about a 50% current efficiency (the output could source or sink about 50% of the supply current), and even a lower power efficiency since, like BFL, this large current goes to -V,,, not to Vss (ground in BFL). This "bufferless" FET logic also generates another problem, that of current differencing. The available load current is the difference between a large pullup current and a large pulldown current such that if the ratio between the currents changes (due to statistical parameter variations or backgating, for example), the available load current drive suffers badly.This problem is even more severe in Schottky Diode FET logic (SDFL, see U.S. Patent No. 4,300,064 and Reference 3, R. C. Eden, B. M. Welch, R. Zucca and S. I. Long, IEEE Tran. Electron Devices, ED-26, No. 4, pp.299317 (1979) or SC-14, No. 2, pp.221-239 (1979) where, because of the use of diode logic, the pulldown loading is heavy, and in fact variable depending on fanout and the logic state of other gate inputs on the loading gates. From a current efficiency stand-point, capacitor-coupled FET logic (CCFL, see A. W. Livingstone and P. J. T. Mellor, 'Capacitor Coupling of GaAs Depletion Mode FET's' 1980 GaAs IC Symposium Abstracts, paper No. 10) is excellent (about the same as DCFL), and allows single-supply operation, but the CCFL gates cannot operate to dc, which is not usually acceptable in logic applications.Further, the published CCFL circuits used reverse-biased Schottky diodes fabricated on the FET channel nlms layer for the coupling capacitors. At the normal operating reverse bias of these diode capacitors, this n;ms layer was pinched off, such that the capacitor structure was very complicated and area-inefficient. Somewhat similar operation, but extended to dc, was obtained by adding a feedforward capacitor to the BFL gate structure (FF-BLF, see M. R. Namordi and W. A. White, IEEE Electron Device Letters, V.EDL-3, No. 9, Sept. 1982, pp.264-267), but at substantial sacrifice in current efficiency and complexity due to the source follower output stage.

Summary of the invention The present invention relates to the use of a capacitor diode-coupled logic gate approach for designing GaAs D-MESFET logic circuits which results in dc to very high speed operation with typically 90% to 97% current efficiency (CDFL gates can source approximately 90%-97% of the supply current and sink up to several times this). Also, this approach does not require the complication of a source-follower output stage on each gate. The CDFL design approach is based on the recognition that in FET logic, the load currents are essentially capacitive. That means that the best voltage shifter element would be a tiny battery integrated on chip between the D-MESFET drains at the FET logic node and the gate output.In the case of pure capacitive loads, there is no net dc power required from such a battery, and, in fact, if the gates of the MESFETs connected to the output occasionally go into forward conduction, then the battery would be charged, not discharged. Inasmuch as no such battery devices are available in integrated circuits at present, a suitable substitute, also requiring minimal power or complication is desired. Accordingly, it is a feature of the present invention to provide a constant voltage shifting circuit for GaAs Integrated circuits that enhances load current drive efficiencies without causing significant signal delay and which has an acceptable size (i.e., does not unduly reduce the gate density of the integrated circuits).Further, the invention provides a number of specific circuit techniques for D-MESFET logic gates including Schottky diode "high" drain clamping and saturation diode 'low' drain clamping which can further enhance logic delay times or transition speeds. Further, the invention provides input circuits using saturation resistor (SATR) Schottky diode clamp techniques in conjunction with CDFL shifting which offer both protection against burnout with gross logic input signal overdrive and tight control of input threshold voltage (even if the MESFET pinchoff voltage is changed due to process variations), such that signal compatibility with conventional silicon bipolar emitter coupled logic (ECL) circuits can be achieved.It is a further feature to provide output circuit techniques featuring Schottky diode 'high' clamping and saturation diode 'low' clamping at the gate input of a source follower output device which enables the circuit to maintain WIRED-OR capability and controlled ECL output signal compatibility over a wide range of load resistance and terminating voltage combinations.

Certain embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 shows a CDFL voltage shifter circuit, Figure 2 shows a typical CDFL NOR gate circuit with an output CDFL level shifter, and Figure 3 shows an ECL-compatible CDFL input/output circuit for a logic inverter.

Turning now to Figure 1, Capacitor Diode FET Logic (CDFL) uses the shifter structure of Figure 1 as a reasonably close substitute for the ideal battery described in the summary of the invention.

The circuit consists of a capacitor (DCAP) 10 which is kept charged to an essentially constant voltage, VSHIFT by a very small current flowing through a chain of three small Schotty diodes 12, 14 and 16.

The small bias current is provided by a very small pulldown current sink PD 18, connected to a negative supply, VEE (VEE needs to be about a volt or greater more negative than the most negative output logic swing, when Vp = -1.0V pinchoff voltage D-MESFETS are used for PD 18).Also Ipd approximately equals Ibas Proper operation of the shifter circuit of Figure 1 is obtained when the capacitance of the shifter capacitor DCAP 10 is much larger than the load capacitance 20 (typically 3X to 10X CLOAD). Under this condition virtually all of the input ac current goes into the load and the high frequency ac voltage gain of the shifter, AViAVIN = CDCAP/(CLOAD + RECAP) approaches unity (0.75 to < 0.9).While other capacitor structures (such as high-e MIM [metal insulator metal) capacitors) could be used to implement DCAP, in the present circuits a special high C/A (capacitance divided by area) reverse-biased Schottky diode structure is used. This device is fabricated on a fairly heavily doped ( > 2 x 1017/cm2) implant of sufficient thickness to ensure it is not pinched off at the normal operating reverse bias (SHIFT is approximately 2.3 volts with a 3-diode shifter). The DCAP capacitance may also be augmented, with no additional expense in chip area, by paralleling the diode capacitance by the MIM capacitance of an additional 2nd level metal layer electrode, connected to the diode cathode, lying on top of the Schottky anode metal but separated by a thin dielectric layer.

This basic shifter structure 22 can be used anywhere in circuits when a level shift is required; in input/output (I/O) circuits, at gate inputs, at gate outputs, etc. A simple 3-input CDFL NOR gate structure using CDFL output level shifter is shown in Figure 2. It is also possible to equivalently locate the CDFL shifters at each gate input so that line interconnection capacitances need not be driven through the DCAP 29, so that the DCAP 29 area may be smaller, but this necessitates making more of the shifter structures since there are typically several times as many gate inputs as gate outputs.

The three drain-dotted (paralleled) D-MESFETs 24, 26 and 28, used to achieve the NOR function in Figure 2, illustrate one CDFL gate configuration. In general, various series-parallel combinations of D MESFETs can be used to realize different logic functions in CDFL, as in other types of FET logic.

The use of dual-gate FETs or series and parallel combinations of FETs to achieve different logic functions in a FET logic gate are familiar to persons skilled in the art, as is the use of other types of load devices such as saturation resistors, gateless FETs, resistors or combinations of these with FETs as the pullup 33 and/or pulldown 35 loads (or 18 in Figure 1 or 56, 58, or 60 in Figure 3). For example, the sink may comprise a D-MESFET with a resistor connected to its source lead. This circuit is shown with the usual power supply potentials for ECL-compatible operation (VDDL = GROUND, VE, = 5.2V as the standard ECL supplies to which we add a Vss = -3.3V supply). In more usual GaAs IC operation this would be shown with Vss = GROUND, VEE = -1.9V (or more negative) and VDDL = +3.3V (or more positive).This circuit, with the particular FET dimensions shown, requires a maximum supply current of (ID55/W) x 16.5 micro meters (W=GATE WIDTH), while it can source up to (it55/ W) x (16.5-1.5 = 15 micro meters), so the current efficiency (sourcing) is 15/16.5 = 91%. The current efficiency in sinking can be several hundred percent (depending on the maximum input voltage), even from a single input.

The CDFL NOR gate structure of Fig. 2 also illustrates another technique developed for GaAs circuits to maintain optimum high speed performance over a wide range of supply voltages (VDDL VSS = 3.3 to 7 volts) if desired. In normal FET logic approaches, the logic high swing is limited by the positive supply voltage (VDDL VSS) through the "softlimiting" action of a pullup active load, PU, going out of drain saturation. As VDDL-VSS is increased, the positive logic swing increases up until the point where the Schottky gates of loading MESFETs go into hard conduction.This latter condition places the MESFETs in an extremely poor fT region of operation (very high gate capacitance, Cgs, with poor transconductance, g/im), degrading performance over and above that caused by the excessive logic voltage swing itself (the switching transition time of a capacitive load, C, at a constant load current, IL, switching through a logic swing voltage AV, is approximately At C, AV,/I,). The use of an optional logic clamp high Schottky switching diode 30, DLCH, to a clamp potential, VLCH, provides hard limiting of the positive logic swing independent of VDDL-VSSS avoiding this performance degradation with changing supply voltage (i.e., increase in AV, with increasing VDDL). The VLCH potential can be obtained from a passive supply (eg. a zener diode alone) since it only sinks current to Vps. An on-chip current sinking voltage regulator supply output can be provided on the chip to supply a nominal VLCH clamp potential.

Of somewhat less importance, but with some capability for performance enhancement is the use of the optional V,c, input 32 to further control logic swings by clamping the logic low level through the optional diode 34. This has the effect of, in addition to reducing delay by reducing AVL, keeping the MESFETs out of the very low VDS (at high V,,) region in which the 7 is poor.This clamp requires an active (power sourcing) supply, however, and hence increases gate dissipation.This could render the use of V,c, impractical if it were simplistically applied, because if all 3 of the input MESFETs 24, 26 and 28 in the gate of Figure 2 were turned on to VE, = +0.8V, the resultant total drain current could, with hard clamping, reach 10 times the active load pullup (PU) current, IDD. This condition is avoided by the use of a special velocity-saturating Schottky diode 34 structure for DLCL which goes into controlled current limiting when the forward current exceeds a specified level. This prevents excessive V,c, current when many parallel logic FETs are "on" simultaneously (eg.FET's 24, 26 and 28 Figure 2), but still gives optimum logic operation by very quickly returning the logic low level to its proper level when some of the gate inputs are turned off. The velocity-saturating diode used for DLCL 34 (and also for DDCL 61 in Figure 3) is a planar Schottky diode structure using the same n implant (using the same technology used in Reference 3) used for the Schottky switching clamp diodes (e.g. 30 of Figure 2, and 40, 42 or 62 of Figure 3).These saturation diodes, however, are designed with carefully controlled periphery of the anode of the diode (Schottky contact) in order to control the maximum forward current, and are also designed such that the current in the metal contacts at this forward saturation current value does not exceed the metal migration limit for the interconnect metal used (J,,, equals approximately 1x106 A/cm2 for gold).The saturation forward current of the velocity saturating diode 34 or 61 is essentially proportional to the anode periphery of the diode (perimeter of the Schottky contact effectively touching the n implant), with the proportionality constant about 1mA of forward saturation current per 1 micrometer of anode periphery for the typical approximately 450 ohm/0n implants used for GaAs IC Schottky switching diodes. In some applications the modest improvements in speed afforded by V,c, use do not justify the added complexity of providing the extra power sourcing potential input and the extra (though relatively small) chip dissipation involved, so that DLCL 34 may be omitted; or if included, a default connection of V,c, to Vss may be used.

While a basic gate structure such as the CDFL NOR gate shown in Fig. 2 can be used to efficiently implement logic within circuits, it will not in general be usable for chip input and output interface applications.GaAs ditigal IC outputs are frequently required to drive transmission line impedances to standard ECL signal levels, while the inputs are to be ECL signal compatible, as well as resistant to damage due to gross signal overdrive, static discharge etc. Figure 3 shows an inverter structure which embodies both the CDFL input and output configurations. The inverter circuit 36 illustrated is unusual in that both chip input and output circuits are on the same stage (on most chips these are separated by a number of logic stages), but the l/O circuit principles are the same.

The signal inputs are protected by a bidirectional current limiter, SATR (saturation resistor or gateless D-MESFET) 38, and clamp diodes DICH (input clamp high diode) 40 and DICL (input clamp low diode) 42 combination which allows up to approximately 40 volt p-p (+40dBm) steady state ac signal levels to be applied without damage or interference with proper circuit operation. The SATR device 38 exhibits low resistance of 30 to 40 ohms at (normal) low applied voltages, but for applied voltages above approximately + IV the device goes into current limiting at an I,,, of approximately + lOmA. (The SATR device may be fabricated in most D-MESFET GaAs IC processes in the same manner as a D-MESFET but omitting the Schottky gate electrode which would normally lie over the n- channel between the n implanted source and drain regions.This "gateless FET" bidirectional current limiter has been discussed in the GaAs IC literature. For simple input protection, default clamp voltages of V,CH=VDD,=0.0V (GROUND) and V,c, =Vss=-3.3V may be used, which limits the internal signal voltages to a safe (but overdriven) +1.2 to -4.5 volt range. This input structure can also be conveniently used to generate regulated internal "square-wave" signal voltages from unregulated sinewave signal sources. This "squaring" is usually done by connecting V,CH=V,C,= 1.3V (the ECL signal threshold), typically using a blocking capacitor in the input signal line to remove any dc component, and then applying a 3Vpp to 20Vpp (+13dBm to +30dBm) sinewave input to give an internal "squarewave" signal of approximately 2Vpp (-0.3V to-2.3V). With normal -0.8V to -1.8V input signal levels, the SATR 38 has virtually no effect on performance due to its low resistance (approximately 5ps delay typically).

The key problem from an input standpoint is maintaining the proper -1.3V input threshold voltage Vth for ECL signal compatible operation over the range of D-MESFET pinchoff voltages normally encountered in GaAs IC manufacture (in excess of Vp=-1.0~0.2V). The key to controlling threshold voltage is to make use of the fact that the shortrange variations in Vp (variations in Vp when measured at distances that are less than about 1 mm apart) are small as opposed to the wafer to wafer variations that are largest (with slow gradations over wafers next in magnitude).Because the pullup (PU) 60 and switching FET 44 widths are unequal, the gate voltage, V,-V,, at threshold is not zero [V,-V,, is approximately equal to Vp(1-(Wpu/ WFET)2L where the FET pinchoff Vp equals approximately -1V is assumed equal for the FET 44, PU 60 and PD 58.Fortunately, this tendency for Vg at threshold to become more negative with increasingly negative Vp is accompanied with a corresponding increase in IPD because of the increased Id,, of the pulldown bias FET PD 58.Considering the finite forward resistance of the shift diode chain 46, 48 and 50, this increase in bias current will increase the shift voltage, Ash,,. Since the input threshold voltage is given as V, (at threshold) plus V,,,,, the result is some degree of cancellation between these two terms. In the CDFL circuits, the shift diode 46, 48 and 50 series resistance and bias levels as determined by the size of PD (pulldown) 58, can be carefully designed to give 1st-order complete cancellation of these terms and hence, to first order, zero change of input threshold voltage with changing V, (again assuming short range FET uniformity so that Vp for FET 44, PU 60 and PD 58 are equal).This first-order cancellation is achieved, assuming square-law (ides= K'W (V,,-V,)2) FET characteristics (where W is the MESFET width and K' is a process constant for the MESFETs) and a series resistance plus ideal logarithmic diode model for the diodes (VF=R,lF + (nkT/q) log,(ll,), where IF is the forward bias current) by equating the change in V,-V,, at threshold (i.e. the value of V,-V,, necessary to make the FET 44 and PU 60 currents identical - see formula above) with V,. The total dynamic resistance, RD, for an N-diode shifter (N=3 in the preferred embodiment) is RD = N (R,+ (nkT/q)/l,), where n is the ideality factor of the diode and kT/q = 0.02585V at T = 300"K.The first-order canceliation occurs when IpDRD = -1/2 (V,-V,,) where IPD = I, is the nominal shift diode bias current and V, -V,, = V,(1- (WPU/WFET)2) is the FET gate voltage at threshold. The balance can be effected by selection of the FET to PU size ratio, or by altering either the bias current (lED) through the shifter (ID,, of the PD 58) or the series resistance of the shift diodes 46, 48 and 50 by altering their geometry (or building a resistor in series with them).Note that by placing a resistor between the source of PD 58 and VEE, the variation of IPD with Vp may be altered. Similar relationships to produce the design independence of VTH with V, in this modified circuit can be derived by one skilled in the art.

The input current to the logic gate would equal the shift diode bias current (approximately 0.2mA typically) if the input pullup current source 56 were not provided. While this level is not too large, for many applications lower input bias current is desirable so the input pullup 56 can be used to null or cancel the shift diode bias current to give less than 100 micro amps net input bias current for the logic gate.

While designing for 1st order independence of gate input threshold voltage with respect to D MESFET pinchoff voltage variations makes manufacturability of circuits compatible with ECL signal levels possible, we would also like, at least for some applications, to have that threshold voltage be temperature independent. The fact that the forward voltage drop at constant current for a diode decreases essentially linearly with temperature (negative temperature coefficient) makes the CDFL shifter structures at first glance a marginal choice for temperature stability. The electron mobility in GaAs, however, varies inversely with absolute temperature (pnaT-1) so that the ohmic resistance of implanted GaAs resistors is proportional to absolute temperature (positive temperature coefficient).

Hence again, with careful device and operating point design it is possible to achieve a substantial degree of cancellation between the junction (-TC) and resistive (+TC) terms to minimize the temperature coefficient of Vsh,ft. Of course, some of the ECL technologies to which the GaAs parts are intended to match, have themselves a substantial temperature coefficient. It is clearly impossible to match all of the wide range of signal level temperature coefficients of these various logic families in one part.

The method of coping with this problem in critical applications is provided by the VTRIM input 52 to the circuit of Figure 3. This potential, normally defaulted to VEE, changes IPD (the shifter bias current), and hence V,,,,, to precisely adjust VE. Given an ECL threshold voltage (V,,), a simple op-amp circuit can be used to generate the VTNIM potential necessary to make the GaAs gate thresholds track the temperature variation of the ECL threshold (V,,). Feedbacks circuitry to generate this VTR!M potential from an external V,, input could be provided on-chip to achieve this threshold tracking.

The principal of this tracking is to input a potential, V,,, equal to the ECL threshold voltage into an equivalent CDFL gate having the same input shifter structure and the same Wpu TO WET ratio so that its input voltage is identical to the active CDFL gate(s) input(s). The operational amplifier is used to feedback a signal to VT,IM in such a manner as to stabilize the output of this gate at its output threshold (this negative feedback configuration would be obvious to someone skilled in the art). The use of the form discussed above wherein a resistor is used between the source of PD 58 and VEE is more convenient for on-chip feedback in that VTEIM will then not be required to be made more negative than VE,, which is usually the most negative potential available on the chip.

The design goals for the CDFL output circuits include capability to drive a wide range of output impedance (RL) terminating voltage (vet) combinations to ECL-compatible signal levels, typically supporting wired-OR (source dotting) logic operations between multiple GaAs gates driving the same node. The biggest problem here is that silicon bi polar ECL circuits are sensitive to overdrive on input logic "highs", since for V,N > -0.6 or -0.5V the input bipolar transistor tends to go into saturation, which greatly degrades its turn-off time when the 'high' is removed.On the other hand, if a MESFET output circuit is sufficiently robust to be able to drive the midpoint of a 50 Ohm transmission line (terminated at both ends, so effectively R, 25 ohms), the required output high (approximately -0.8V) drive current may exceed 50mA, while with high impedance lines (eg. 100 ohms to -2Vrr), only about 25% of this current is required (approximately 12 to 17mA). Because of the finite output impedance of the gate (approximately 12.5 ohms), this will tend to overdrive the high output levels when low-current load combinations are used, which can degrade ECL circuit performance unacceptably.

The output configuration used to solve this problem is shown in Figure 3. The basic output device is a large (the gate width W typically equals approximately 600 micro meters or larger) source follower 54 with its drain connected to a 0.0V (or positive) VDD supply, VDDO (separate from VDDL to avoid crosstalk interference). The gate drive to source follower 54 can be from a high value of nearly VDDL to a low value slightly above V,,, which is sufficient to cut off essentially all output current in source follower 54 at typical -2V output levels (using V,,=-3.3V with Vp=1.0V MESFETs) allowing for WIRED-OR output operation.The size of the source follower 54 allows it to source (depending on Vow', VDDD, and VoDL) over 80mA (70mA continuous rated); with VDDO=VDDL=VDCH=0 an output high appears as an approximately 12.5 ohm resistance to VDDO=OV. This allows excellent output load drive capability, but means that with high impedance loads, the output high voltage level, VDH, will be higher than optimum for ECL (eg. with R,=100 ohms to VTT=-2V, VDH equals approximately -0.25V).

The driver clamp high potential, VDcH, can be used to hardlimit the positive gate drive (through the onset of forward conduction of the Schottky diode DDCH 62) to source follower 54, eliminating this problem.This passive (power sinking) VDCK supply (typically on the order of VDCH= 1.75V) is selected for the particular load R, and VTr combination used.

While use of the VDCH upper clamp potential can be necessary for maintaining ECL output compatibility, that is not generally the case for the VDCL lower clamp supply, since silicon bipolar ECL circuits are not sensitive to negative signal overdrive.

The optional VDCL (driver clamp low) supply (operating through the onset of forward conduction of the velocity saturation diode DDCL 61) can be provided to allow for performance optimization, particularly with large negative Err values (eg. V,=- 3.3V or -5.2V), in a similar manner to the V,c, potential discussed earlier (Figure 2). As with V,c,, the use of the VDCL supply will increase the chip power dissipation slightly, but use of the special velocitysaturating Schottky diode structure discussed earlier for DDCL 61 (Figure 3) minimizes this effect.

The capacitor diode-FET logic circuit approach achieves load current efficiencies in D-MESFET digital circuits approaching those of enhancementmode circuits. The approach is simple and straightforward and allows for excellent device parameter tolerances without substantial degradation of yield or performance. While the shift capacitor (DCAP) area required adds to the CDFL gate area somewhat, the area penalty is small and the resulting circuit areas, while higher than SDFL, are comparable to other FET logic circuit approaches implemented with D-MESFETs (eg. BFL). The CDFL approach also lends itself to the implementation of threshold-controlled I/O structures such as the ECL I/O circuits discussed in conjunction with Figure 3.

ThepeFfQ17ance achieved in CDFL gates is of the order of dc to 3GHz operation in input, logic, and output circuits. The I/O circuit of Figure 3 can give, fully clamped, input to output logic delays from a terminated 50 ohm line input, through the input protection and shift circuitry, through the logic stage and through the output driver into a 50 ohm line, as low as 75 pico seconds. Conventional NOR gate-implemented edge-triggered D-FF's fabricated in a standard 1 micro meter gate length GaAs IC process have shown clocking frequencies of 3GHz or toggle frequencies of 3GHz in divider configurations.The CDFL circuit approach, though with modified supply levels, has also been used, in conjunction with a slightly more exotic flip flop architecture (using dual-gate and series-parallel logic FET combinations to achieve complementary AND/NOR and OR/NAND - gate configurations) to achieve, in a single (not complementary) clock input divider, a rated 4GHz maximum toggle frequency.Considering that a GaAs divider, providing .2, +4, t8, +16+32, +64, and .128 high speed outputs in an 100 gate complexity MSI circuit, operating at up to a 3GHz clock rate, dissipates only about 600mW, (exclusive of the load VTT power for whichever output or outputs are used - typically 25 to 40mW each, depending on V, and R,), it is clear that these CDFL GaAs IC's offer exceptional performance with minimal power requirements.

While the preferred embodiments of the present invention have been described and illustrated, various modifications will be apparent to those skilled in the art and it is intended to include all such modifications and variations within the scope of the appended claims.

Claims (15)

1. A fixed electrical potential shifting device for passing AC signal current comprising: a bias means connected in parallel to a capacitance means wherein the parallel combination of said bias means and said capacitance means are connected in series with a sinking means for providing a controlled voltage shift between an input and an output in a semiconductor integrated circuit.

2. A device as claimed in claim 1 wherein said semiconductor integrated circuit is a GaAs device.

3. A device as claimed in claim 1 or 2 vvherein said bias means comprises at least one Schottky diode and said capacitance means comprises a high capacitance per unit of area reverse-biased Schottky diode.

4. A device as claimed in claim 1 or 2 wherein said capacitance means comprises a high capacitance per unit of area reverse-biased Schottky diode in parallel with a MIM capacitor means formed by a Schottky metal contact to said diode and a second level metal electrode connected to said diode's cathode, said MIM capacitor means lying over said Schottky metal contact but separated from it by a thin insulated layer.

5. A device as claimed in any preceding claim wherein said sinking means is a D-MESFET.

6. A device as claimed in claim 5 wherein said sinking means is a D-MESFET with a resistor connected to its source lead.

7. A fixed voltage device comprising a bias means connected in parallel to a capacitance means wherein the parallel combination of said bias means and said capacitance means are connected in series with a sinking means.

8. A device as claimed in any preceding claim wherein said bias means and said capacitance means are connected to a clamping means and a saturation resistor means for protecting logic circuits from high input voltage swings.

9. A protection means for protecting a semiconductor input comprising a clamping means connected to a saturation resistor means for protecting logic circuits from high input voltage swings.

10. A negative voltage swing limiting device comprising a saturation diode connected to a current source means and a switching means for reducing a negative potential excursion when said switching means is in a conducting mode.

11. A positive voltage swing limiting device comprising means and a switching means for reducing a positive potential excursion when said switching means is in a nonconducting mode.

12. A GaAs output voltage swing limiting device comprising a Schottky diode connected to a current source means, a switching means and an output driver means for limiting the positive output voltage level.

13. A GaAs output voltage swing limiting device comprising a saturation diode connected to a current source means, a switching means and an output driver means for limiting the negative output voltage level.

14. A depletion mode MESFET integrated circuit having a voltage shifting circuit comprising capacitance means connected between circuit input and output points, biassing means connected in parallel with said capacitance means for supplying a substantially constant biassing voltage to said capacitance means, and current sinking means connected to said biassing means for sinking a biassing current passing therethrough.

15. An integrated circuit substantially as hereinbefore described with reference to any of the Figures of the accompanying drawing.