FR2535062A1 - DIGITAL MEMORY OSCILLOSCOPE WITH ANALOG SHIFT REGISTER - Google Patents

Abstract

THE INVENTION RELATES TO A DIGITAL MEMORY OSCILLOSCOPE INCLUDING AN ANALOGUE SHIFT REGISTER, AN ANALOGUE-DIGITAL CONVERTER, A DIGITAL WAVEFORM MEMORY, A DIGITAL-ANALOGUE CONVERTER AND A DISPLAY. THE TECHNICAL PROBLEM IS TO BE ABLE TO WORK ACCORDING TO A LARGE NUMBER OF DIFFERENT MODES DEPENDING ON THE SETTING OF THE TIME BASE. ACCORDING TO THE INVENTION, A PAIR OF CHARGE TRANSFER ELEMENTS 22A, 22B, IN PARALLEL OPERATING IN ROLL SCAN MODE, REAL-TIME SCAN, EXTENDED REAL-TIME DIGITIZATION AND EQUIVALENT TIME DIGITIZATION, IS USED. TIME BASE SETTINGS. APPLICATION TO THE ANALYSIS OF WAVEFORMS.

Description

"Digital memory oscilloscope with a decimated register

Analog lage ".

  The present invention generally relates to a digital storage oscilloscope, and more particularly to a single mode of acquiring and displaying an analog input signal using a pair of shift registers.

analog in parallel.

  The digital storage oscilloscope is one of the types of waveform analyzers used for digitizing an input analog signal and storing digital data for later display.

  of the waveform of the analog signal or of a par-

  a digital computer or a microcomputer These oscillo -

  opes with digital memory are more and more successful because

  unique characteristics such as the post and the pre-

  clipping, infinite storage time and many signal processing that can not be achieved with oscillo

  Usual scoops in real time, this being in addition to digital techniques

  such as increasing the sample rate-

  swimming (scanning) and memory capacity at a reduced price.

  In addition, printed circuit technologies and LSIs have introduced high speed analog memory units, such as charge transfer devices,

  at an extremely reasonable price.

  It is therefore an object of the present invention to provide

  an advanced digital memory oscilloscope with

  an analog shift register.

  This is yet another object of the present invention

  to provide a digital storage oscilloscope that can work

  valiant according to a lot of different modes depending

setting of the time base.

  Yet another object of the invention is to provide an improved display method and apparatus for

  a digital storage oscilloscope.

  It is yet another object of the present invention to provide a digital memory oscilloscope comprising a

single slider mode.

  The digital memory oscilloscope according to the invention

  is of the type comprising analog shift register members, an analog-to-digital converter,

  of digital memory of waveforms, a digital-to-digital

  Analog and a display member According to the invention, as analog shift register members, a pair of parallel load transfer elements used in the real-time scanning mode (roll), digitizing

  in real time extended and scanning in equivalent time depending on

  setting of time base settings.

  According to another characteristic of the invention, the

  The display gantry further includes a cursor generator

  to generate at least one mode of accelerated displacement of

  sor. According to yet another characteristic of the invention, the display members comprise a cursor generator for generating at least one cursor for each waveform channel, the cursors of the two channels being able to be aligned or controlled by

independently.

  Other features and advantages of the invention

  will be apparent from the following description, made with reference to the

  drawings appended hereto, in which: FIG. 1 is a simplified block diagram of a digital storage oscilloscope according to the present invention; Fig. 2 is a detailed block diagram of the analog shift register portion;

  FIGS. 3 to 6 are simplified block diagrams

  and explanatory waveforms for explaining the four basic modes of operation according to the present invention; Figs. 7 and 8 are circuit diagrams of important parts associated with the analog shift register circuits;

  Fig. 9 is a block diagram of the circuit-of

  which can be used according to the present invention; fig 10 is a flow chart of the cursor operation

? 535,062

  Fig. 11 is a block diagram of a cursor control circuit;

  Fig. 12 is a graph that represents the location of

  slider as a function of time; Fig. 13A and Fig. 13B are waveform displays showing the sliders, and

  Fig. 14 is a CRT display explaining

  the command of the trigger position to use

  in the digital storage oscilloscope.

  Fig 1 is a block diagram of an oscilloscope

  two-channel digital memory device according to the present invention.

  Input signals are applied through

  respective input terminals 1 Qa and 1 Ob to a pre-amp circuit

  12 which includes programmable attenuators 14a and 14b and input amplifiers 16a and 16b. This pre-amplification circuit 12 attenuates the input signals according to the setting of the control circuit 52 which is described below. and

  it converts these signals into differential output signals.

  Differential output signals from the circuit

  Pre-amplification cook 12 is applied to a circuit of

  analog shift registers 18 which includes circuitry for

  20a and 20b and charge transfer elements, charge transfer elements 22b and 22b, output amplifiers with charge transfer elements 24a and 24b, a switch 25,

  an analog-to-digital converter 26 and a generator of

  Sampling 28 Attack circuits * selected for trans-

  20 a and 20 b amplify the input signal to drive the charge transfer elements respectively.

  22a and 22b which may include a pair of parallel chains

  load transfer elements with, for example, 445

  The charge transfer elements 22a and 22b receive timing information from a timing circuit 48 which will be described below for capturing samples of the respective input signal under the control of the sampling generator. 28 whose frequency can vary -4- for example between 200 kHz and 20 M Hz The outputs from the charge transfer elements 22a and 22b are amplified by output amplifiers with 24a and 24b charge transfer elements. b, and applied via the switch 25 to the analog-to-digital converter 26 to digitize these

  samples in a manner that will be described below.

  The memory circuit 30 includes a waveform memory 32 for storing the entered waveform data from the analog-to-digital converter 26 of the

  circuit with charge transfer elements 18 The memory of

  wavelength 32 is controlled by a control circuit and

  synchronization 34 A display circuit 36 comprises a

  digital-to-analog converter 37, a vertical amplifier 38, a horizontal amplifier 39 and a display control circuit 40 A digital-to-analog converter 37 receives

  analog display signals that control the amplifi-

  The display control circuit 40 controls the display modes of the waveform data stored on a display device 42 which includes visual display means such as for example a tube cathode ray The control circuit of the display

  also provides an intensity control signal to the

  positive display 42 for cursor display or other operations. Trigger circuit 44 includes trigger generator 45 and trigger control 46 Trigger circuit 44 is a circuit for generating trigger gate signals that provide a trigger reference point at a time base to be described further. The trigger generator 45 receives internal trigger signals from the input amplifiers 16a and 16b and external trigger signals from

  an external trigger terminal 47 or a signal of de-

  line triggering from a line terminal The trigger control circuit selects the trigger level, -5-

  the trigger slope and the trigger coupling modes

  (direct current, alternating current, bass rejection

  frequencies, rejection of high frequencies, etc.).

  The timebase circuit 48 provides the synchronization

  Basic setup for the digital storage oscilloscope and includes a clock generator 39 and a controller

  of the time base mode 50 The time base circuit 48 re-

  receives setting and control information from a

  microprocessor 54 and in turn transmits back to the micropro-

  processor 54 of the trigger and timing data for use in setting the microprocessor and controlling the memory circuit 30 and the display circuit 36 The microprocessor performs, among other things, such calculations as the average value of the signal and measurements The feed circuit 56 comprises different

  57 for the different electrical circuit blocks.

  and a control circuit of the attenuator relay 58

  for controlling programmable attenuators 14a and 14b.

  According to a preferred embodiment, the time base circuit comprises four basic modes of operation

  "roll" or scrolling that allows to follow continuously the evo-

  slow phenomenon, real-time digitization, digital

  real-time real-time scanning and equivalent time scanning.

  These modes of operation are determined automatically by the setting of a "split time" switch disposed in the front panel 52. The "roll" operating mode is selected in the range of 20 S to 100 m S of the switch. division time, the real-time scanning mode in the range of 50 m S to 500 ES, the extended real-time scanning mode in the range of 200 ES to 2 g S and the operation mode in equivalent time in the range from 1 μ S to 50 n S In the first three operating modes, an entire waveform is captured during an acquisition cycle. However, in the equivalent-time scanning operation mode, a form of wave -6-

  composite consists of one or more samples

  lons taken during several scans in a similar way

  to that used in conventional oscilloscopes

  matching time This means that the form of on-

  is in real time in the first 3 operating modes but is not in real time in the last mode of operation Each operating mode will be described in

detail below.

  As shown in FIG. 2, the load transfer element circuit 22 is constituted by a pair of parallel analog shift registers, each of which can contain 455 cells. Channel A samples the negative side.

  differential input signal from the amplifier of

  switch 20 to 5 charge transfer elements while channel B

  samples the positive side of the input signal when

  receive sampling clock signals A and B on their respective charge injection gates For each sample clock pulse from channel A (or B),

  takes a sample of the signal and stores it in the first

  first cell of the analog shift register.

  following clock pulses, this sample is shifted from cell to cell until the 455 th clock pulse for which this sample is sent to the output amplifier

  and consequently to the analog-digital converter 26

  of the switchable amplifier 24 The circuit with

  Load transfer devices 22 can operate in two modes

  different: simultaneous differential sampling and sampling

Alternate differential logging.

  FIG. 3 represents a simplified form of the "roll" operating mode. In this mode, the two channels A and B of the charge transfer elements 22 receive clock signals.

  at the same pace and with the same phase in order to sample simul-

  the positive and negative sides of the output signal of the differential amplifier 20 this helps to provide a larger output signal to the analog-to-digital converter 26

7 2535062

  while suppressing the common-mode signal such as noise, drift, and losses of the charge transfer elements The charge transfer element circuit 22 continuously samples the input signal at a constant rate, for example at a frequency of 400 kHz Only the samples selected from the digital analog converter are then stored in a given memory block, for example 1024 (1 K) words of the waveform memory 32 in the memory circuit. a frequency determined by a sampling counter which is set by the microprocessor 54 such that a given number of samples (eg 100) per division is displayed on the cathode ray tube display of the device 42 For example, for the setting corresponding to 0.1 S per division of the

  time switch by division, the samples are stored

  in the waveform memory 32 at a rate of 1 kHz.

  Thus, all 400 th samples that the elements to be trans-

  22 input charge are stored in the waveform memory 32 because the charge transfer elements 22

  sample at 400 kHz in this particular example.

  When the 1023 th memory location of the waveform memory 32 is filled, the memory circuit cyclically returns to the zero location, so that one

  treats the memory of waveforms 32 as an infinite register

  The display circuit 36 scans the waveform memory 32 continuously with change of the start point in the waveform memory 32 for each new display cycle. The display on the CRT is set updated continuously with the 1024 samples acquired the most

recently (see Fig. 3 (B)).

  The mode of operation in real time digitization is represented in FIG. 4. In this mode, the charge transfer elements 22 also continuously sample the input signal at a constant rate (for example 400 kHz) and memorize data. selected samples of the signal in a block of a K of the waveform memory 32, also at a rate determined by the sampling counter.

  when the trigger generator 45 recognizes the trigger

  memorization of the continuous waveform samples

  until we reach a pre-selected count of post-

  triggering, counting which is set by means of the control 52 of the front panel, and at this moment the acquisition of signals is stopped In the post-triggering account, one includes the

  compensation for the time of 455 samplings by

  load transfer devices 22 The post-trip position

  chosen determines which part of the signal is memo-

  in a first block of 1 K of the waveform memory

  32 in relation to the occurrence of the triggering.

  wave is stored in the waveform memory 32, the timebase is reset and another form is entered

  similarly, but this waveform is

  in a second 1K block of the waveform memory 32 using the switch 51 The first waveform is displayed on the cathode ray tube 42 by means of the switch 52 while the second waveform is captured. This process is repeated continuously by switching the switches 51 and 52 in one direction and the other between the two blocks of 1 K of the waveform memory 32, so that the display of the waveform memory 32 is always displayed. part of the signal that has been acquired most recently.

  The extended real-time scanning mode is

  Fig. 5 Firstly, a selected portion of the signal is entered into the charge transfer elements 22A and 22B and then written to the waveform memory 32.

  real-time scanning mode, the component channels

  22 A and 22 B charge transfer

  continues the input signal at a rate that is determined by

  the setting of the "time / division" switch When the genera-

  Trigger 45 recognizes the occurrence of a tripping

  The charge transfer elements 22A and 22B continue to sample the signal for a predetermined number of post-trip counts after which the sampling operation is stopped. Samples blocked in the charge transfer elements 22 A and 22 B are then written in a first block of 1 K of the wave formon memory E at a rate of 400 kHz As soon as the waveform is stored in the waveform memory 32, the base of

  time is reset and a new form of on-

  As for the real-time scanning mode described above, the second waveform is written in a second 1K block of the waveform memory 32 and the circuit

  display 42 shows the waveform acquired most recently.

  is lying. In the extended real-time scanning mode, the charge transfer elements 22 A and 22 B sample

  the signal at a rate that is faster than the one at

  which data is entered in waveform memory 32 This signal acquisition mode is called

  fast entry, slow exit (fast-in, slow-out) Both

  22 A and 22 B sample the signal in a slightly different way from the one used.

  in the real-time scanning operation mode.

  That is, charge transfer element channels

  22 A and 22 B sample the signal simul-

  For example, on the rising edge of the clock pulse as in the other modes, but in the extended real-time digitization mode, they take alternate samples of the signal, the load-transfer element 22A sampling a sample on the rising edge of the clock pulse,

  while the load transfer element 22 B takes a sample of

  This technique is used to effectively increase the signal sampling capability in real time while maintaining the above-mentioned advantages of paralleling the transfer elements of the clock pulse. charge The part of the waveform that can be acquired in this mode depends on the

2535062

  combined length of the two charge transfer elements 22 A and 22 B (910 samples) The time resolution for the extended real-time scanning operation mode can be reduced to, for example, 80 samples per division rather than 100 samples in other modes. In the equivalent-time scanning operation mode which is shown in FIG. 6, a composite waveform is produced in a 1 K block of the memory of FIG.

  forms of wave 32 from a plurality of acquisition cycles

  This is because the charge transfer elements 22 are unable to capture enough samples in a waveform acquisition cycle. In other words,

  the frequency of the input signal increases too much

  te for charge transfer elements 22 which can not capture the required number of samples to reconstruct the waveform of such a signal in a single acquisition cycle of

  waveform Several samples are captured for a number of

  successive acquisition cycles until an accurate composite representation of the waveform is

  in memory of waveforms 32 To determine o memo

  In the case of samples seized during other acquisition cycles, the time base 50 of FIG. 1 measures the time interval.

  between the onset of the trigger and the immediate

  according to the microprocessor 54 so as to memorize

  to make the samples of each acquisition cycle

  correct memory placements of waveform memory

  32 Due to the asynchronous nature of the input signal (

  triggering) and clock signals, such

  time correction is necessary to obtain a

  correct presentation of the signal waveform

  that the rate of the sampling clock is prede-

  Once completed, it is sufficient to calculate only a first sample of each acquisition cycle. Alternatively, a time shift of the display unit's position offset position 2535062 can be used as described in the French patent. No. 02 464 479 It should be noted that the equivalent time digitization mode can only be used for repetitive input signals. FIG. 6B represents samples acquired while FIG. 6C represents a combined waveform reproduced on FIGS. FIG. 7 shows the circuit diagram of an exemplary charge transfer element driving amplifier 20. Transistors Q 1 and Q 2 constitute an input differential amplification stage. with emitter coupling resistors R 1 and R 2 and a transistor Q 3 constituting a current source Transistors Q 4 and Q 5 on the one hand and Q 6 and Q 7 on the other hand constitute two offset stages of nive which form a differential cascode amplifier in combination with the transistors Q 1 and Q 2 The voltage gain of this amplifier is approximately

  determined by the resistors R 1 to R 6 The resistance R 5 is

  to achieve a particular gain adjustment.

  sistors Q 8 and Q 9 constitute an error correction stage which compensates for the gain variations of the amplifier which are

  due to compression and thermal distortion of the signal.

  Transistor Q 8 amplifies and inverts a portion of the positive half (+) and adds it to the negative half (-) of the signal at the summing node on the emitter of transistor Q 7.

  positive signal (+) increases in amplitude, we add more

  error correction signals to the negative (-) signal, which creates

  a linear gain The transistor Q 9 operates in the same way.

  The resistance R 7 is chosen at an appropriate value in relation

  with the resistors R 1 and R 2 to obtain the minimum distortion

  The atomel amplifier A 1 is used to maintain

  a constant output voltage on the collectors of the tran-

sistors Q 6 and Q 7.

  FIG. 8 is a diagram of the circuit of the output amplifier 24 of the charge transfer elements and of the switching circuit 25 of FIG. 1. The amplifiers 24 a and 24 b are identical to each other for the essential and only the amplifier

12 2535062

  24 a is shown in detail It comprises a pair of stages

  Q 10 and Q 1 i emitter-follower amplifiers for

  staggered-buffers for load transfer elements

  22A and 22B, and a controllable gain Q 12 and Q 13 differential amplifier comprising a transistor Q 14 constituting a current source A potentiometer Rg is used to make

  precise adjustment of the gain of the two elements with charge transfer

  The voltage gain of the differential amplifier Q 12-Q 13 is essentially determined by resistors R 10 and R 11, but a gain control circuit is used which comprises a pair of voltage transistors. field Q 15 and Q 16 'of the operational amplifiers A 10 and A 1 il and resistors R 12 to R 21 to compensate for the gains of the charge transfer elements 22 A and 22 B The gain control technique is similar to that described in US Patent No. 03,710,270 A pair of field effect transistors Q 15 and Q 16, which are tuned and coupled in a single capsule, act as resistors

  variables while the resistors R 16 to R 21 including the trans-

  field effect sistor Q 16 form a bridge circuit An ampli

  The operational indicator A 10 compares the zero voltage of the ampli-

  differential calculator Q 12 -Q 13 on the common terminal of the resistors R 14 and R 15 with the voltage of the terminal common to the resistors R 16 and R 17, the output voltage of the amplifier A 10 being sent to the resistors R 16 to R 19 and also to the series resistors R 20 and R 21 The amplifier A 11 compares the bridge voltages on the common terminals of the resistors R 17 and R 18 on the one hand and R 20 and R 21 on the other hand, the output of this amplifier

  being supplied to the two gates of the transistors Q 15, Q 16.

  The gate voltage of the transistors Q 15 and Q 16 varies in such a way that the bridge circuit remains balanced, which provides a constant sourcedrain resistance for the two transistors Q 15 and Q 16 for a given condition of the bridge regardless of the different temperatures. resistance may vary

when R 19 varies.

  The switching circuit 25 comprises two pairs of Q 17 to Q 20-based transistors connected to the collector of the transistors Q 12 and Q 13. Obviously, similar transistor pairs are included in the circuit 24 b of the channel 2. Resistors are used. R 22 to R 25, an operational amplifier A 12 and diodes D 1 and D 2 for maintaining the emitter voltage of transistors Q 17 to Q 20, and hence the collector voltage of transistors Q 12 and Q 13 at a given voltage lower than the collector voltage of the transistor

  Q 14 mounted in current source transistors Q 21 to Q 24 con-

  There are two additional pairs of transistors, Q 5 and Q 26 on the one hand, and Q 27 and Q 28, on the other hand, and a NOR logic gate G constitute a control circuit of a switch. reference voltage

  is applied to the transstoe bases Q 26 to Q 28 Lots of the fonrc-

  When either of the two terminals 60 and 62 or both is at the logic high level, the NOR logic gate G provides a low level output, which causes the blocking of the transistor.

  Q 25 and conduction of the transistor Q 26, which activates the transistors Q 17 and Q 18 in the channel 1 The output of the charge transfer element 22 a of the channel 1 is then selected and coupled

  an analogue-digital converter 26 for the purpose of

  A mirror circuit comprising transistors Q 21 to Q 24

  is used to make maximum use of both push-out

  pull (differential) from the collector of transistor Q 18 '

  By their own, when the terminal 62 is at the low level, the

  Q 27 and Q 26 sistors are blocked and the transistors Q 28 and Q 25 are conductive, which leads to the choice of the output of the

  load transfer elements of channel 2 The output of

  load-transfer systems of channel 1 is effectively canceled

  1 and Fig. 9 shows a detailed schematic diagram of the display circuit 36 of Fig. 1. This circuit controls the display mode: YT (voltage), and is short-circuited to ground through transistors Q 19 and Q 20 '. as a function of time), XY, -14 -

  reading and cursor The display cycle command, the ef-

  eradicating and reading digital data from the

  waveform memory 32 are other functions of this circuit.

cooked display 36.

  64 data interlocking circuits

  mode receive adjustment data from the middle of the

  microprocessor 54 through its data bus and distribute this data to different circuit blocks included in the circuit 36 and other related circuits. A display clock receives timing information from the time base 48 which is used to synchronize the display circuit with the X-read and Y-read time slots of the memory This clock also produces horizontal scan clock pulses which are used

  to digitally generate a horizontal ramp signal

  A display length counter 66 counts the horizontal scan clock pulses and provides a digital horizontal ramp which is constituted by a series of digital numbers that sequentially increase from zero to

  a number, for example 1024 A logic circuit of com

  display 67 decodes the outputs of counter 66 of long

  display to start and end the business cycle.

  A temporary locking circuit in X68 and a

  temporary locking circuit in Y 69 receive respectively

  X and Y data from the waveform memory 32 via a waveform data bus

  The Y data is then applied to a

  vertical digital digital weaver and an erase logic circuit 71 The X data is applied to an X data multiplication and locking circuit 72 which

  selects either the X data from the memory of

wavelength 32, which is digital ramp data from the display length counter 66 and which applies these

  data to a horizontal digital-to-analog converter 73.

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  The clear logic circuit 71 controls the erasure of the cathode duallow electron beam. It also provides an automatic erase of the beam at the end of each display cycle and an erase between data points in the read mode. vector 74 is used selectively to display a continuous waveform

  by joining the neighboring points in a virtual display mode

  This filter is shunted in a dot display mode.

  An analog display bus multiplexer 75 applies the mode control data of the latch circuits 64

  mode control data and vertical and

to the microprocessor 54.

  The operation of the display circuit 36 will now be described with reference to Fig. 9 In the YT mode, data for the Y-axes from the waveform memory 32 of the memory circuit 30 are supplied to the converter. The display length counter 66 generates data for the X-axis which represents a digital ramp signal which is applied by the digital-to-analog vertical circuit 70 via the Y data latch circuit 69. intermediate of the locking and multiplexing circuit 72 data in

  X to digital-to-analog converter 73 Analog outputs

  converted into Y and X from converters 70

  and 73 are displayed according to a point at coordinates corresponding to

  on the display system 42 is in the virtual mode.

  either in the dot mode after the necessary amplification.

  The display length counter 66 and the plurality circuit 72 are

  tipxing and locking X data are receiving

  clock pulses at the same rate as the generator of

  display stands in the memory circuit to display a series of points with equal horizontal spacing possibly reproducing the waveform

  of the input signal on the screen of the cathode ray tube.

  The X-Y mode is similar to the Y-T mode just mentioned except that the 16-axis waveform data -

  X's from the waveform memory 32 are substituting

  killed at the X-axis ramp data That is to say that

  the X-axis data read from the memory of

  Means 32 during a reading time interval X are latched in the latch circuit 68 of X-time data and, similarly, the Y-axis data read from the waveform memory 32 during a read time slot of Y are latched in the Y data latch circuit 69. The latched X and Y data are applied simultaneously to the respective% -convertors 70 and 73 respectively. The data X and Y are the data respectively. of the waveform of channel 1 and

  channel 2 The display cycle continues until the com-

  length of the display length has reached its maximum count.

  mum thus displaying the waveform plot (channel

  1) against another waveform (channel 2).

  Reading mode is a variant of the X-Y mode Reading data such as characters and numbers

  representing memory waveform positioning commands

  settings, trigger settings, time difference measurements (time difference between cursor points on the displayed waveform), are stored in the form memory

  as X-Y coordinate series (matrix points).

  This data is then read to the display circuit 36 and latched in the data latches 68 and 69. They are displayed on the CRT screen during a display cycle as in the XY mode. Such data is generally displayed on the upper sides and

  lower screen of the CRT.

  The last mode (cursor mode) is intended to indicate one or two slider points on the eu or on both of the waveforms displayed for accurate measurements of time (time difference) and this mode is also a variant of

  X-Y mode The microprocessor 54 determines the horizontal position

  zontal cursor on the display This or these slider points

17 2535062

  can be displayed using a few different techniques.

  According to one embodiment of the invention, the microproces-

  54 is a waveform which is composed only of data points arranged at the cursor position. The stored waveform data is displayed either in XY mode. or in YT mode as described above But when starting the cursor mode, the data stored in the microprocessor 54 are displayed repeatedly in a time-sharing mode by displaying the slider points with a reinforced level ( brighter than the other points) Alternatively,

  the cursor position data is stored in the memory.

  memory chip (RAM) of the microprocessor 54 in order to be compared

  a digital comparator with the contents of the counter 66 of

  display or data lock circuwt be.

  When the two numerical data coincide, the output of

  comparison is applied to the control grid of the cathode

  to modulate the intensity of its beam.

  Thanks to the previous description, we can now

  distinguish the four basic modes of operation of the display circuit. We will now describe below with more than

details, the cursor mode.

  In the Y-T waveform display mode, for example, each waveform includes a given number of sampling points. If the sampling density is 100

  sampling divisions, 1000 sampling points consis-

  form a complete waveform Because the points of cur-

  Depending on the waveform displayed or the types of measurement, it is not easy to locate one or more cursors numerically at the precise memory locations that are desired in a minimum of time. in

  U.S. Patent No. 03 843 873 can be applied for this purpose.

  But, the use of a rotary control occupies a large space on the control panel which is already overloaded Thanks to the slider display according to the present invention, only two small push buttons are used to control

  a digital member such as a reversible counter.

  Fig. 10 shows a flow chart showing

  the counter is controlled. Su and Sd cursor up and down buttons are used to count or count the count in the counter First, check if the Su (or Sd) button is enabled If Su (or Sd) is pressed, the counter of a stage is advanced from the current count.

  synchronization means measure the length of time for determining

  whether or not Su (or Sd) is continuously activated for more or less long Tr If the activation time

  t is greater than T 1, a series of pulse pulses is applied.

  lodges at a first rate on the counter by making advance the counter at this first rate If the duration t is greater

  at T 2 (T 2 being larger (read T 1), the clock rate is

  core increased to a second rate, which makes the counter advance at a faster rate Similarly, the

  the aforementioned activation time is compared with constant values

  preset to further increase the clock rate, which speeds up the cursor movement until Su (or Sd)

  either released or deactivated when the cursor approaches the

  desired placement of the waveform.

  Fig. 11 shows a block diagram of an embodiment of the cursor generator. A reversible counter 76 is a ten-stage (10-bit) counter which can count or count down according to the command which is provided by the control device of the controller. slider 77 which includes buttons

  up and down the counter Su and Sd A detecting element

  78 is used to know whether either Su or Sd is enabled.

  A delay circuit 80 measures the duration of activation "t" of the pushbutton Su or Sd under the control of a clock generator 81. The control circuit 80 controls the clock rate control circuit 82 which provides pulses 19 -

  output at different rates depending on the time of ac-

  Thus, the counter 76 counts or counts in the preprogrammed accelerated manner and the final count is stored in a predetermined memory location in the microprocessor RAM 54.

  For example, four locations of

  memory in the RAM for cursor data (two

sliders for each waveform).

  It should be noted that the counter 76 can be replaced by an accumulation register and the circuit of

  controlling the clock rate 82 by an incident register.

  The content of this latter register is controlled by the micropro-

  cesseur 54 as a function of the aforementioned activation time and added

  or subtract from the register depending on the activation of Su or Sd.

  Fig. 12 shows a graph showing position versus time, how the cursor is moved

  from the current location (coordinate A) to the new location

  Desired cement D When either Su or Sd is activated at instant to, the cursor advances one stage and begins to move in an accelerated manner for a time T 1 (t 1 t O = T 1) until the moment t 2 o Su or Sd button is off Cursor location at time T 2 is designated B and is near destination D Activates cursor button again for a shorter period (t 2 t 3) to further advance the cursor to a location C which is very close to D On then repeatedly activates the button Su or Sd to move up or down to location D at a time tn If the location

  B is close enough to D, we can move the cur-

  down or forward to the D position by omitting the intermediate operation (t 2 t 3) If the location C has passed the other side of the destination D, we obviously use a

  step-by-step approach process

  Fig. 13 shows examples of display of cur-

  on waveforms Figure 13A is an example in the-

  which the two waveforms of canl 1 and channel 2 include two cursors at corresponding locations This display mode - with cursor is called the "aligned" cursor display which is

  particularly useful when both waveforms are

  This cursor mode is achieved by reading the same cursor data from both waveforms or by storing the same cursor data for the two memory locations. In addition, the slider display is also displayed. effective to observe the waveform of channel 1 alone and then observe the waveform of channel 2 while maintaining fixed cursor points Fig 13 B is an example of an independent cursor mode

  in which two cursors are displayed for each waveform.

  Obviously respective cursor data is stored

in the memory.

  Fig. 14 shows waveforms displayed to explain the trigger command of the oscilloscope

  digital memory device according to the present invention.

  shift registers or load transfer elements

  allows the operator to select either a pre-trigger mode

  either a post-trigger mode or a mix of these.

  two triggers The pre-triggering relates to a trigger mode in which the waveform of the signal present before the occurrence of the trigger is displayed.

  the post-trigger is a trigger mode in the-

  which one displays the waveform of the existing signal after the

  triggering, which is the mode available in conventional oscilloscopes By controlling the amount of modes

  pre-triggering or post-triggering, one can posi-

  the occurrence of triggering at any location

  However, it is difficult and complicated to select the position of the waveform to be displayed on the cathode ray tube screen. This problem can be solved by intentionally using the characteristics of each waveform including a given number of data points by horizontal division, for example, 100 samples per division irrespective of the settings of the switch "time 21 - by division1" The occurrence of the trip must be displayed at the leftmost frame line when the position of

  trigger is set to the zero scale line, but this

  the position shifts to the right of a division when the position of the trip switch is increased. For example, the trip position will be displayed in the center of the CRT at position 5 TRIG 5) as shown by the solid line in FIG. 14 On the contrary, the appearance of

  trigger will move to the left of a horizontal division

  zontale by decreasing the trip position even beyond the leftmost frame line in the mode to

  post-triggering As indicated above, the pre-trigger

  or the post-trigger are selected by controlling the signal acquisition time in relation to the recognition

  triggering is selected Pre-triggering if read

  quisition of the signal and writing in the waveform memory

  32 are stopped when recognizing the appearance of the

  In addition, the post-trigger mode will be obtained if only the waveform data is memorized when recognizing the occurrence of the triggering. For example, if the writing of the acquired waveform data is not stopped until 100 samples of waveform data are stored in the waveform memory

  32 after the occurrence of the trigger in the pre-de-

  triggering, the occurrence of the trigger will be displayed at the second frame line from the left Thus, the trigger position is implemented to add or subtract the numerical setting from a constant number (for example 100) each time trigger position control is activated, which causes the trigger point to be shifted along the entire screen of the CRT by actuating

only ten times the button.

  As described above, the digital memory oscilloscope according to the present invention uses a pair of parallel analog shift registers per channel, a digital analog converter, a digital waveform display, and a display unit They are operated according to four different modes scroll (roll), scanning in real time, scanning in

  extended real-time and equivalent time scanning

  setting the time base settings The shape data

  are stored in the digital waveform memory.

  that at a rate such that the displayed waveform comprises a predetermined number of data samples by division for each of the "time by division" switch settings; This facilitates control of cursor position and triggering. The present invention also includes a unique control of accelerated cursor positioning and trigger position control. The cursor data can be independent for each channel or aligned for both channels. the cursor is accelerated as a function of the activation time but is incremented by a single level for the minimum time of the slider in the direction of

  the desired location, which allows a very precise adjustment.

  In the trip position control, the trip position is moved at each horizontal division and such a setting is digitally displayed on the display screen.

  cathode ray tube for the convenience of the operator.

  The above description of exemplary embodiments

  of the invention has been provided for illustrative purposes only and

  restrictive and it is understood that modifications or variations can be made without departing from

of the present invention.

23 -

Claims (2)

  ) Digital memory oscilloscope with a   analog shift register, an analog converter   a digital memory of the form of the on & b, a converts   digital-to-analog converter and a display member characterized by using a pair of charge transfer elements (22a, 22b, 22A, 22b) in parallel as offset registers Analog, running in roll mode, real-time scanning, extended real-time scanning, and equivalent-time scanning depending on settings of the time base.   2) Oscilloscope with digital memory according to the   1, characterized in that the display member comprises a cursor generator for generating at least one mode   accelerated movement of the cursor.   ) Digital memory oscilloscope according to the   1, characterized in that the display member further comprises a cursor generator for generating at least one cursor for each waveform channel, said cursors for each channel being aligned or controllable by independently.