GB2095935A - Apparatus and method for digitization of fast analog waveforms - Google Patents

Abstract

An analog waveform is written onto a semiconductor imager surface eg C.C.D. imager 6 using a CRT2, the charge being transfered column by column to serial register from which it is read by sense amplifiers 18 and digitized at 19. The resultant digital information can then be stored indefinitely and mathematically manipulated before being used, such as for display as a fast storage oscilloscope. <IMAGE>

Description

SPECIFICATION Apparatus and method for digitization of fast analog waveforms This invention is concerned with apparatus and method for digitization of fast analog waveforms.

Digitizing or converting an analog voltage into a digital word is accomplished with analog-to-digital (A/D) converters. The conversion function can be performed in a wide variety of ways. In the prior art, this conversion function is achieved, inter alia, as follows.

Tracking Converter In a tracking or servo type A/D converter, a binary up-down counter is used to generate a binary output which, in turn, drives a digital-to-analog (D/A) converter in feedback around a differential comparator.

This scheme is shown in Figure 1A. The system counts the input clock pulses starting from zero, and the count is converted to an analog voltage VO by the D/A converter. This analog volage is compared to the actual analog voltages VO and VA are equal, the comparator switches and terminates the count. The binary counter digital output then corresponds to the analog input voltage. For full-scale digital output, this type of converter suffers the disadvantage of being slow, since (2N - 1) clock cycles need to be counted, N being the number of bits in the digital word.

Staircase Converter The staircase converter is a simplified version of the tracking converter. Instead of an up-down counter, a simple binary counter is used. In each conversion step, the counter is reset to zero to start counting the clock pulses. This process creates an output from the D/A converter that has the appearance of a staircase. Hence, the name staircase converter. Like the tracking converter, this converter stops counting when its output equals the analog input voltage. Its last count, therefore, corresponds to the digital word for the analog input. This type of converter exhibits the same disadvantage of slowness as the tracking converter. Furthermore, this converter resets iself to zero after every conversion step; this further adds to its slow response.

Successive-Approximation Converter This type of converter approximates the analog input by successively trying a digital ONE in each successive bit of a feedback D/A converter, starting with the most significant bit. A block diagram of such a system is shown in Figure 1 B. In the first step of conversion, a ONE is tried. If the actual analog voltage is greater than the converted analog voltage, and the comparator output remains unchanged, ONE is retained. If less, it is replaced by a ZERO and a ONE is tried in the next bit. In this manner, the approximation process continues until all bits are calcuated. At the beginning of each conversion cycle, the holding register is set to zero, and the complete conversion sequence is repeated. This converter requires complicated circuitry for implementation, and it also suffers from slowness.

Ramp Comparator Converter Figure 1 C shows an example of an indirect AID converter: the ramp-comparator or pulse-width modulator converter. At the start of a conversion cycle, cycle switch S1 opens and capacitor C1 charges with a constant current 1a, thereby generating a ramp voltage V5 where V5 = (lj/Ci)t, t being the charging time. At the instant S1 opens, the counter is activated and starts to count the incoming clock pulses. The counter continues its counting until the ramp voltae V5 is equal to the analog input voltage VA. The comparator stops counting then, and the last count in the binary counter corresponds to the digital word for the analog voltage.

In this type of a converter, (2N - 1) clock pulses must be counted to obtain a full-scale output of N-bits. Although this type of converter is simpler than other types to implement it has a very slow conversion rate.

Simultaneous Converters Simultaneous or parallel A/D converters are, by far, the fastest converters. This type uses a separate analog comparator with a fixed reference for every quantization level in the digital word, from zero to full scale. Then, the outputs of these comparators are appropriately interconnected to produce a parallel digital output. Figure 1D shows an example of such a prior art system. For N-bit resolution, (2N- 1) separate comparators and separate reference levels are needed. Thus, this system exacts a price of high complexity for speed in conversion.

The speed limitation and/or high complexity of the prior art A/D converters place an upper operating limit to the systems in which they are used. This is especially evident, for example, in the high speed digital storage oscilloscopes of the prior art, where the upper operating limit is approximately 1 Gigahertz. The digital storage oscilloscope employs AD converters in its system to convert or digitize the analog input waveform into a digital signal that is stored, for example, in a semiconductor memory.

This stored digital signal is then converted back to analog form for display on a conventional CRT. This method is illustrated Figure 5. If the AID converter cannot operate above 25 megasamples per second, for example, then the system employing it is limited to 10 megahertz; any signal extending beyond 10 megahertz will not be accommodated.

Since the oscilloscope is one of the basic tools in the electronic industry, it would be very advantageous to have A/D circuits operating above 10 megahertz incorporated into the oscilloscope for higher frequency capability.

The present invention provides apparatus for the digitization of analog waveforms comprising CRT means having a fiber optic phosphor faceplate for applying an incident image to a semiconductor imager means in response to an applied input analog signal; semiconductor imager means abutting the fiber optic faceplate of said CRT means for receiving and capturing said image and for providing at least one image signal in response to said incident image; and support circuitry means coupled to said semiconductor imager means for providing support signals to said semi-conductor imager means and for processing said image signal to produce at least one digital output signal.

In apparatus as set forth in the last preceding paragraph, it is preferred that said image signal contains image intensity information and said support circuit means includes a sensor means for sensing said intensity information for providing an output intensity signal.

In apparatus as set forth in the last preceding paragraph, it is preferred that said sensor means is an analog-to-digital converter and said output intensity signal is a digital electrical signal.

Apparatus as set forth in the last preceding paragraph may further comprise an optic fiber plate mounted on said semiconductor imager means for channeling said incident image from said CRT means onto said semiconductor imager means.

Apparatus as set forth in the last preceding paragraph but one or the last preceding paragraph but two may further comprise an optic fiber plate mounted on said semiconductor imager means for channeling said incident image from said CRT means onto said semiconductor imager means.

Apparatus as set forth in the last preceding paragraph but one or the last preceding paragraph but four may further comprise memory means coupled to said support circuit means for storing said at least one digital output signal; processor means coupled to said memory means for conditioning said stored digital output signal in a select manner to produce at least one display signal and display means coupled to said processor means for receiving and visually displaying said at least one display signal.

Apparatus as set forth in the last preceding paragraph but one may further comprise memory means coupled to said support circuit means for storing at least one of said digital output signal and said intensity signal; processor means coupled to said memory means for conditioning at least one of said digital output signal and said intensity signal in a select manner to produce at least one display signal; and display means coupled to said processor means for receiving and visually displaying said at least one display signal.

In apparatus as set forth in the last preceding paragraph but one, or the last preceding paragraph but two, it is preferred that said display means is a television receiver. Alternatively the dislay means may be a CRT system.

The present invention further provides a method of digitizing analog waveforms comprising the steps of illuminating an analog waveform on a fiber optic faceplate; abutting a semiconductor imager device having a plurality of photo-sensitive elements to said fiber optic faceplate, whereby said illuminated waveform activates the photosensitive elements abutting immediately thereto; and reading said plurality of photosensitive elements in a select order to determine the activated photosensitive elements, thereby forming a digital output signal representative of said analog waveforms. A method as set forth in the last preceding paragraph, for waveforms having a wide bandwidth, may further comprise the step of displaying said digital output signal representative of said analog waveform.

A method as set forth in the last preceding paragraph may further comprise the step of processing said digital output signal prior to the step of displaying it.

A method as set forth in the last preceding paragraph but one, for waveforms having a wide bandwidth, may further comprise the step of sensing the light intensity of each of said activated photosensitive elements to form an intensity output signal.

The new A/D converter in accordance with the preferred embodiment of the present invention overcomes the disadvantage of limited bandwidth of the converters in the prior art and offers this advantage; a fast digital storage oscilloscope employing such an A/D converter does not have the speed limitation of the prior art oscilloscopes. It has the ability to capture, digitize, process, and display waveforms of analog signals in the Gigahertz range, even though they may occur at a low duty cycle or as a single event. Furthermore, these waveforms can be indefinitely stored in digital form without deterioration with time. The stored waveforms are available at a later time for processing to yield such information as Fourier transforms, power spectral density, cross power spectra, polar and rectangular coodinates, correlation function, transfer function, coherent output power, and more.After processing, the information can be leisurely displayed for visual analysis, such as on a conventional CRT, a television receiver, and the like.

In accordance with the preferred embodiment of the invention, the analog-to-digital converter uses a semiconductor imager, such as buried channel charge-coupled device (CCD) imager, for almost instant quantization of an analog signal for digitization. Specifically, using semiconductor imagers in the present embodiment of the converter enables analog signal in the Gigahertz range occurring at low duty cycle or as a single event to be digitzed for later processing or display. This represents a substantial improvement in performance over the AID converters and, in turn, the storage oscillocopes in the prior art.

A semiconductor imager typically operates as follows. When light representing an image is incident upon an array of semiconductor elements on the imager, the light is detected by the semiconductor elements, because the element exposed to light is charged. The array of elements is in an X-Y matrix.

Thus the mosaic formed by the charged elements in the matrix is a representation of the incident image.

By clocking the elements out in sequence and detecting the presence or absence of a charge on the elements, an electrical signal representing the image is obtained.

Furthermore, because the charge in the element is proportional to intensity or the amount of incidient light, digitizing the charge information and processing that data can give information about the center of the trace forming the image. This way of determining the waveform is more accurate than that determined simply by the number of charged elements in the X-Y matrix. The other words, the exact analog waveform can be extrapolated from a series of points into a fine line so tht the focus (or the lack thereof) of the incident image on the semiconductor imager becomes unimportant.

Intensity information can also serve to enhance the quality of the image signal. In a semiconductor imager, certain pixels may be activated even though no incident image is present. This can be due to possible defects in the semiconductor device. As a result, the imager will give a less than completely dark signal in the absence of an incident image. This is the "dark signature" of the device. The dark signature of the image can be derived from the digitized intensity information. Storing the dark signature of the imager and subtracting if from an image signal, then, upgrades the quality of the image signal by removing the fixed pattern noise due to the dark signature.

If the imager is clocked continuously without ever stopping the clocks, then the dark values for all picture elements or pixels in a row (or in each half of a row when using the dividend architecture as in the preferred embodiment to be described later) is the same. Hence it is only necessary to store one dark value for each row (or half row).

A CCD imager makes a suitable semiconductor imager in the preferred embodiment of the invention. It is implemented in a buried channel NMOS CCD technology with two levels of polysilicon clock clock lines and front side illumination. This CCD imager technology typifies a good compromise semi-conductor imager where light sensitivity, low signal capacity, and simplicity are simultaneously achieved.

An analog-to-digital converter in accordance with the preferred embodiment of the invention uses a semiconductor imager, for example, a CCD imager to convert an image of an analog signal projected thereon into an electrical signal. To generate and project the image onto the semiconductor imager, a small-spot cathode-ray tube (CRT) is used. The electron beam within the CRTtraces an image on a phosphor face of the CRT. The phosphor face of the CRT is made up of fiber optic plate with a deposit of phosphor elements on one face of the place. Hence, when the analog signal is traced on the phosphor face as an image, the image is transferred outside the CRT on the outside face of the fiber optic plate. In this way, the image, when transferred, does not get diffused and remains relatively sharp and clear.By placing the semiconductor imager in contact with the fiber optic plate so that the transferred image impinges on the imager array, the semiconductor imager can receive the projected image. Additionally, another fiber optic plate can be mounted directly on the face of the semiconductor imager as part of the imager package. This imagerfiber optic plate can be brought into direct contact with the fiber optic plate of the CRT for ease and effectiveness in channeling the transferred image to the semiconductor device. The optic fiber plates provide good coupling efficiency of the light being transmitted from the CRT phosphor face plate. Since the semiconductor imager is photosensitive, the image projected is detected by the individual photosensitive elements comprising the semiconductor imager array.With conventional circuitry, the individual array elements can be read or queries in sequence to arrive at a digital signal representing the applied analog signal for storage and further processing.

There now follows a detailed description which is to be read with reference to Figures 2, 3, 4, 6 and 7 of the accompanying drawings, of an A/D converter according to the present invention; it is to be clearly understood that this converter has been selected for description to illustrate the invention by way of example and not by way of limitation.

In the accompanying drawings: Figure 2 shows the interfacing of a semiconductor imager device with a CRT in accordance with the present invention; Figure 3 shows a representation of a semiconductor imager chip device and the associated registers and amplifiers located on the chip; Figure 4 illustrates a cross-section of a buried channel NMOS CCD imager device; and Figures 6 and 7 show preferred embodiments of a fast digital storage oscilloscope using the prefered embodiment of an analog-to-digital converter in accordance with the present invention.

As shown in Figure 2, a preferred embodiment of an analog-to-digital converter in accordance with the invention is implemented by using a CRT 2 with a small diameter electron beam 4 to write a waveform across the surface of a semiconductor imager array chip 6. The chip 6 is mounted outside the CRT envelope, and a fiber optic faceplate 10 to the CRT 2 and a fiber optic "window" 8 to the semiconductor chip 6 are used to couple the light output from a phosphor layer 11 of the CRT 2 ont the imager chip 6.

The semiconductor imager chip 6 can be implemented in a buried channel NMOS CCD technology with two levels of polysilicon clock lines 12 and front side illumination 14 as shown in Figures 3 and 4. These two levels, or layers, or polysilicon lines are herein designated polysilicon I 12Aand polysilicon II 1 2B to distinguish them. This technology offers a good compromise between light sensitivity, low signal capability, and simplicity. With these characteristics, the CCD imager chip can be used as the semiconductor imager chip 6 to produce a fast analog-to-digital converter. This fast converter, in turn, can be used to produce a fast storage oscilloscope with a high writing speed.

A two-phase clocking scheme 11,13 is to be used for clocking out the signal charge because of its compatibility with the double polysilicon process and because of the ease of clock signal generation.

Buried channel CCD's exhibit higher transfer efficiency and higher frequency operation than surface channel structures. A self-aligned boron implant underthe polysilicon II layer 12B is used to form a barrier region. This increases the charge handling capability of a single storage well which is formed under the polysilicon I layer 12A.

The CCD imager, as the semiconductor imager, does not need light shielded transport registers to prevent picture smearing. The light is incident upon the array of imager elements for only a short period of time. During this time, the clocks are stopped or the image can be exposed quickly so that the clocks do not appear to be moving. The exposure can be controlled by varying the current of the electron beam. As a result, light shielded transport registers are not required and the structure of the light sensing area can be reduced to an array of parallel CCD registers 14.

Figure 3 shows a CCD array divided into two halves along a vertical centerline. The polysilicon lines are connected such that the charge is clocked horizontally, starting from the center of the chip and emanating to the sides. The charge is transferred column by column into high speed serial registers 16 which run along each side of the array of semiconductor imager elements. Therefore, the signal charge representing an image undergoes a parallel to serial transfer. For each slow parallel clock cycle, many fast serial clock cycles are made to occur.* In the preferred embodiment, illustrated in Figure 3, there are two sense amplifiers 18 on the imager chip 6. One sense amplifier is at the end of each serial register 16. This divided architecture reduces the time needed to clock out the charge buckets from all the semiconductor imager elements, or pixels.

The dark charge of each bucket is cut in half and the root-mean-square standard deviation of that charge is greatly reduced.

When writing an analog waveform on the imager surface, the time axis is horizontal and parallel to the CCD channels. Therefore, each of the coiumns of pixels represents one time sample. The analog charge buckets are serially clocked out one column at a time. By processing the charge signature of a column, the beam position on the vertical axis, which is proportional to the signal voltage, can be determined to a high degree of accuracy.

A unique centerline design shown in Figures 3 and 4 divides the imager into two halves while maintaining the periodicity of the array. The center polysilicon il line 15 is connected to the two adjacent polysilicon I lines 17 and 19. The remaining polysilicon land II lines 12A and 1 2B are paired such that the charge is marched away from the centerline.

The horizontal CCD channeis intersect the vertical serial register at a right angle. Transfer of a column of charge from the parallel array to the serial register is achieved by extending every other polysilicon II gate of the serial register until it overlaps the last polysilicon I line of the parallel array. This structure guides the charge packet around the corner and prevents charge in the serial register from reentering the parallel array.

At the output of the serial shift register, the charge flows into a resettable floating sense diffusion. The last cell is separated from the sense diffusion by a polysilicon II gate at a fixed potential. This reduces the capacitive coupling between the serial clocks and the amplifier input.

As an example of an oscilloscope using the analog-to-digital converter in accordance with the preferred embodiment of the invention, Figure 6 illustrates a high speed digital storage oscilloscope.

Analog input signals are fed into input ports Y1, Y2 or Y3 or combinations thereof. The signals control the electron beam in a CRT 2, which describes the image on a semiconductor imager 6 forming part of the A/D converter in accordance with the preferred embodiment of the invention. The charge signal from the image elements of the semiconductor imager chip 6 flows into the two sense amplifiers 18, only one of which is shown in Figure 6 for simplicity.

The amplitude of the output of the sense amplifier 18 is digitized by an A/D converter 19. The digital output is fed to a digital subtraction circuit 20 in which the dark signature of the imager chip 6 is subtracted. The result of the subtraction is fed to a circuit 21 which defines the center of the illuminated trace on the imager surface to a resolution which is finer than the size of a pixel. An optimal center vaiue for each imager column is then stored in a memory 29.

A microprocessor 31 controls data transfer and obeys commands from external suces such as keyboard, control buttons, and a rotary pulse generator 33. It issues control signals for sensitivity, offset, sweep speed, trigger control, etc. The processor 31 can also perform data processing and data retrieval from the memory 29 for display on a display CRT 37.

Because all signals are stored in memory before they are displayed, the display section of the oscilloscope can operate at its own refresh rate, which needs only to be fast enough to avoid flicker. Hence, the display CRT 37 has ample time to wite its own grid, including labelling of axes plus other alphanumerics and cursors on the display. A sweep generator may be added for displaying waveforms.

A different embodiment of a fast storage oscilloscope using the A/D converter in accordance with the preferred embodiment of the invention is shown in Figure 7. Therein, the entire contents of the imager chip 6 is stored in a read-write memory 39. With this system, it is possible to write several waveforms on the imager ship before the contents are transferred into memory. This is accomplished by clocking out the waveforms only after several waveforms have been impressed on 5 the imager chip. The complete picture of all the waveforms, including grid and labelling, can then be displayed, for example, on a display CRT 37 using a raster scan.

Claims (15)

1. Apparatus for the digitization of analog waveforms comprising: CRT means having a fiber optic phosphor faceplate for applying an incident image to a semiconductor imager means in response to an applied input analog signal; semiconductor imager means abutting the fiber optic faceplate of said CRT means for receiving and capturing said image and for providing at least one image signal in response to said incident image; and support circuit means coupled to said semiconductor imager means for providing support signals to said semiconductor imager means and for processing said image signal to produce at least one digital output signal.

2. Apparatus according to claim 1 wherein said image signal contains image intensity information and said support circuit means includes a sensor means for sensing said intensity information for providing an output intensity signal.

3. Apparatus according to claim 2 wherein said sensor means is an analog-to-digital converter and said output intensity signal is a digital electrical signal.

4. Apparatus according to claim 1 further comprising an optic fiber plate mounted on said semiconductor imager means for channel said incident image from said CRT means onto said semiconductor imager means.

5. Apparatus according to either one of claims 2 and 3 further comprising an optic fiber plate mounted on said semiconductor imager means for channeling said incident image from said CRT means onto said semiconductor imager means.

6. Apparatus according to either one of claims 1 and 4further comprising: memory means coupled to said support circuit means for storing said at least one digital output signal; processor means coupled to said memory means for conditioning said stored digital output signal in a select manner to produce at least one display signal; and display means coupled to said processor means for receiving and visually displaying said at least one display signal.

7. Apparatus according to claim 5 further comprising: memory means coupled to said support circuit means for storing at least one of said digital output signal and said intensity signal; processor means coupled to said memory means for conditioning at least one of said digital output signal and said intensity signal in a select manner to produce at least one display signal; and display means coupled to said processor means for receiving and visually displaying said at least one display signal.

8. Apparatus according to either one of claims 6 and 7 wherein said display means is a television receiver.

9. Apparatus according to either one of claims 6 and 7 wherein said display means is a CRT system.

10. Apparatus for the digitization of analog waveforms substantially as hereinbefore described with reference to Figures 2,3,4,6 and 7 of the accompanying drawings.

11. A method of digitizing analog waveforms comprising the steps of: illuminating an analog waveform on a fiber optic faceplate; abutting a semiconductor imager device having a plurality of photosensitive elements to said fiber optic faceplate; whereby said illuminated waveform activates the photosensitive elements abutting immediately thereto: and reading said plurality of photosensitive elements in a select order to determine the activated photosensitive elements, thereby forming a digital output signal representative of said analog waveform.

12. A method according the claim 11 of displaying analog waveforms having a wide bandwidth and further comprising the step of: displaying said digital output signal representative of said analog waveform.

13. A method according to claim 12 further comprising the step of processing said digital output signal prior to the step of displaying it.

14. A method according to claim 11 of displaying analog waveforms having wide bandwidth further comprising the step of sensing the light intensity of each of said activated photosensitive elements to form an intensity output signal.

15. A method of digitizing analog waveforms substantially as hereinbefore described with reference to Figures 2, 3, 4, 6, and 7 of the accompanying drawings.