GB2128858A - Digital storage oscilloscope - Google Patents

Abstract

A storage oscilloscope samples differential signals (10), loads the samples into CCD analogue registers (22), converts some or all outgoing samples to digital (26) and stores them in memory (32) whence they are read, converted to analogue (37) and displayed (42). According to the timebase period selected, one of four modes is adopted, termed Roll, Realtime digitizing (RD), Extended realtime digitizing (ERD) and Equivalent time digitizing (ETD), for successively shorter timebase periods. Roll The memory when full overwrites earlier records. In successive display scans the starting point moves on in memory to give a slow 'roll'. RD Continuous sample stream passes along CCD, a fraction being stored in double buffer memory. Trigger causes sampling to stop after further selected number, allowing display while the second buffer is filled. ERD As RD but CCD samples much faster than memory write. ETD For repetitive waveforms only. Samples come from different cycles; for each the time to the next sample after the trigger event is measured by time base so that waveform can be built up in memory. The two channels may be shown against time (XvT, VvT) or against each other (YvX). Cursors in several modes may be provided. <IMAGE>

Description

SPECIFICATION Digital storage oscilloscope Background of the invention This invention pertains generally to a digital storage oscilloscope, more specifically to a unique way of acquiring and displaying an input analog signal by using a pair of parallel analog shift registers.

A digital storage oscilloscope is one kind of waveform analysis apparatus for digitizing an input analog signal and storing the digital data for future display of the analog signal waveform or calculation by a digital computer or a microcomputer (lip). Such digital storage oscilloscopes are gaining popularity because of unique features such as post-and pretriggering, infinte storage time and various signal processings not attainable by conventional realtime oscilloscopes, in addition to advanced digital technologies such as increased sampling (digitizing) rate and memory capacity at reduced price.

Additionally, IC (integrated circuit) and LSI (large scale integration) technologies have brought about high speed analog memory devices such as CCDs (charge coupled devices) at a fairly reasonable price.

It is therefore an object of this invention to provide an improved digital storage oscilloscopes incorporating an analog shift register.

It is another object of this invention to provide a digital storage oscilloscope operating in a plurality of different modes depending on the timebase setting.

It is still another object of this invention to provide a unique way of operating analog shift registers.

It is yet another object of this invention to provide an improved display method and apparatus for a digital storage oscilloscope.

It is an additional object of this invention to provide a digital storage oscilloscope with a unique cursor mode.

It is a further object of this invention to provide a dual channel digital storage oscilloscope with an aligned and independent cursor generator.

These and other objects of this invention, as well as its operation and advantages will become apparent to those skilled in the art upon a reading the following description when taken in conjunction with the accompanying drawings.

Drawings Figure lisa simplified block diagram of the digital storage oscilloscope according to this invention; Figure2 is a detailed block diagram of the analog shift register section of this invention; Figure 3 through 6 are simplified block diagrams and explanation waveforms for explanation of four basic modes of operation of the present invention; Figures 7 and 8 are circuit schematics of important parts associated with the analog shift register circuit; Figure 9 is a detailed block diagram of the display circuitry to be used in this invention; Figure 10 is a flow chart of cursor operation; Figure 11 is a block diagram of a cursor control circuit; Figure 12 is a graph showing cursor location versus time.

Figures 13A and 13B are waveform displays showing cursors; and Figure 14 is an explanatory CRT display for the trigger position control to be used for the digital storage oscilloscope.

Detailed description of the invention Figure lisa simplified block diagram of a dual channel digital storage oscilloscope according to this invention. Input signals are applied through respective input terminals 10a-l0bto preamplifier circuitry 12 including programmable attenuators 14a-14b and input amplifiers 16an166. Preamplifier circuitry 12 attenuates the input signals according to the setting of control circuitry 52 described hereinafter and also converts such signals into differential output signals.

The differential output signals from preamplifier circuitry 12 are applied to analog shift register circuitry 18 which comprises CCD drivers 20a-20b, CCD 22a-22b, CCD output amplifiers 24a-24b, switch 25, analog-to-digital converter (ADC) 26 and strobe generator 28. CCD drivers 20a-20b amplify the input signal thereto for driving respectively CCDs 22a-22o which may include a pair of parallel CCD chains with, for example, 445 stages. CCDs 22a-22b receive timing and synchronization information from timing circuitry 48 described hereinafter to take samples of the respective input signal under control of strobe generator 28, the frequency of which may vary, for example, between 200 KHz and 20 MHz.The outputs from CCDs 22a-22b are amplified by CCD output amplifiers 24a-24b and applied through switch 25 to ADC 26 for digitizing such samples in a manner to be described later.

Memory circuitry 30 includes waveform memory (WFM) 32 to store the acquired waveform data from ADC 26 in CCD circuitry 18. WFM 32 is under control of control and synchronization circuit 34. Display circuitry 36 includes digital-to-analog converter (DAC) 37, vertical amplifier 38, horizontal amplifier 39 and display control circuit 40. DAC 37 receives digital display data from WFM 32 and converts it to analog display signals which drive vertical and horizontal amplifiers 38 and 39. Display control circuit 40 controls display modes of the stored waveform data on display system 42 including visual display means such as, for example, a cathode ray tube (CRT). Display control circuit 40 also provides an intensity control signal to display system 42 for cursor display or other operations.

Trigger circuitry 44 comprises trigger generator 45 and trigger control 46. Trigger circuitry 44 is a circuit to generate trigger gate signals which provide a trigger reference point to a timebase described hereinafter. Trigger generator 45 receives internal trigger signals from input amplifiers 16a-16b, and external trigger signal from EXT terminal 47 or a line trigger signal from a LINE terminal. Trigger control circuit 46 selects trigger level, trigger slope, trigger coupling modes (DC, AC, LF reject, HF reject, etc).

Timebase circuitry 48 provides the basic timing for the digital storage oscilloscope and includes clock generator 49 and timebase mode control 50. Timebase circuitry 48 receives setup and control information from microprocessor FP 54, and in turn transmits trigger and timing data back to AP 54 for use in setting FP and controlling memory circuitry 30 and display circuitry 36. FP 54 performs, among other things, calculations such as signal averaging and delta-time and delta-voltage measurements.

Power supply circuitry 56 includes various power supplies (P/S) 57 for operating various electric circuit blocks and also attenuator relay drive circuit 58 for driving programmable attenuators 1 4a-1 4b.

In one preferred embodiment, timebase circuitry 48 has four basic modes of operation: roll, realtime digitizing (RD), extended realtime digitizing (ERD) and equivalent time digitizing (ETD). These modes of operation are determined automatically by the setting of a time-per-division switch in front-panel section 52. The roll mode of operation is selected in the range of 20S to 100 mS of the time-per-division switch, the RD mode of operation in the 50 mS to 500 liS range, the ERD mode of operation in the 200 FS to 2 FS range, and the ETD mode of operation in the 1 FS to 50 nS range. In the first three modes of operation, an entire waveform is captured during one acquisition cycle.In the ETD mode of operation, however, a composite waveform is built up from one or more samples taken during a number of sweeps in a manner similar to that used in conventional equivalent time sampling oscilloscopes. This means that the captured waveform is realtime in the first three modes of operation but not realtime in the last mode of operation. Each mode of operation will be described in detail hereunder.

Firstly, as shown in Figure 2, CCD circuitry 22 is a pair of parallel analog shift registers, each of which may contain 455 cells. Channel A samples the minus side of the differential input signal from CCD driver amplifier 20 while channel B samples the plus side of the input signal upon receiving sampling clock A and B at their respective charge injection ports. On each sampling clock to the channel A (or B), a sample is taken of the signal and is stored in the first cell of the analog shift register. On subsequent clocks, this sample is shifter from cell to cell, until on the 455th clock, it is applied to the output amplifier and subsequently to ADC 26 by way of switchable amplifier 24. CCD circuitry 22 may be operated in two different modes: simultaneous differential and alternate differential samplings.

Figure 3 shows in a simplified form the roll mode of operation. In this mode, both channels A and B of CCD 22 are clocked at the same rate and phase to simultaneously sample the plus and minus sides of the output signal from differential amplifier 20. This helps to provide a larger output signal to ADC 26 while canceling the common mode signal such as noise, drift, and leakage of the CCDs. CCD circuitry 22 continuously samples the input signal at a constant rate, e.g. 400 kilohertz rate.Only selected samples from ADC 26 are then stored in a given memory block, e.g. 1024(1 K) K) words of WFM 32 in memory circuitry 30 at a rate determined by a sample counter which is preset by pwP 54 in such a manner that a given number of samples (e.g. 100) per division will be displayed on the CRT display in system 42. For example, at the 0.1 S/DIV setting of the time-per-division switch, samples are stored in WFM 32 at a rate of one kilohertz. Thus, ever 400th sample that CCD 22 takes is stored in WFM 32 because CCD 22 is sampling at 400-kilohertz in this particular example. When the 1023rd memory location of WFM 32 filled, memory circuitry wraps around to location 0, such that WFM 32 is treated as an infinitely long register.Display circuitry 36 scans WFM 32 continuously, changing the start point in WFM 32 for each new display cycle. The CRT display is continuously updated with the 1024 most recently acquired samples (see Figure 3 (B)).

The RD mode of operation is shown in Figure 4. In this mode, CCD 22 also continuously samples the input signal at a constant rate (e.g. 400 kilohertz), and stores selected samples of the signal in a 1 K block of WFM 32, again at a rate determined by the sample counter. However, when trigger generator 45 recognizes the trigger, the storage of waveform samples continues until a preselected post-trigger count preset by front-panel control 52 is reached, at which time signal acquisition is halted. Compensation for the 455-sample delay through CCD 22 is included in the post-trigger count. The post-trigger position selected determines which portion of the signal is stored in a first 1 K block of WFM 32 with respect to the trigger event. Once the waveform has been stored in WFM 32, the timebase is reset and another waveform is acquired in the same manner.

This waveform however, is stored in a second 1 K block of WFM 32 by using switch S. The first waveform is diaplayed on the CRT 42 by switch S2 while the second waveform is being acquired. This process is repeated continuously by switching S1 and S2 back and forth between the two 1 K blocks of WFM 32, such that the most recently acquired portion of the signal is always displayed.

The ERD mode is shown in Figure 5. A selected portion of the signal is first captured in CCDs 22A-22B and then written in WFM 22. In the ERD mode, the CCD channels 22A-22B continuously sample the input signal at a rate determined by the time-per-division switch setting. When trigger generator 45 recognizes the trigger event, CCD 22 continues to sample the signal for a preset number of post-trigger counts, at which point sampling operation is discontinued. The samples held in CCD 22 are then written into a first 1 K block of WFM 32 at a 400-kilohertz rate. Once the waveform is stored in WFM 32, the timebase is reset and anotherwaveform is acquired. As with the RD mode described earlier, the second waveform is written into a second 1 K block of WFM 32, and display circuitry 42 displays the most recently acquired waveform.

In the ERD mode, CCD 22 samples the signal at a much faster rate than the acquired data is written into WFM 32. This mode of signal acquisition is called fast-in, slow-out. Both CCD channels 22A-22B sample the signal in a slightly different way in the ERD mode of operation. That is, CCD channels 22A-22B take a sample of the signal simultaneously, for example, on the leading edge of the clock as in the other modes, but in the ERD mode they take alternate samples of the signal, CCD 22A taking a sample the leading edge of the clock while CCD 22B taking a sample on the trailing edge. This technique is utilized to effectively increase the realtime signal sampling capability while maintaining the aforementioned advantages of the parallel CCD scheme.The portion ofthewaveform that can be captured in this mode is dependent on the combined length of both CCDs 22A-22B (910 samples). The time resolution in the ERD mode of operation may be reduced to, for example, 80 samples per division rather than 100 samples in other modes.

In the ETD mode of operation as shown in Figure 6, a composite waveform is built up in a 1 K block of WFM 32 from a pluralityofwaveform acquisition cycles because CCD 22 is unable to take enough samples in one waveform acquisition cycle. In other words, the input signal frequency increases too high for CCD 22 to take the required number of samples to reconstructthewaveform of such signal in a single waveform acquisition cycle. More samples are taken on a plurality of subsequent acquisition cycles until an accurate composite representation of the waveform is built up in WFM 32.In order to determine where to store the samples in WFM 32 with respect to samples taken during other acquisition cycles, timebase 50 in Figure 1 measures the time interval between the trigger event and the next subsequent sample by the aid of pP 54, thereby storing the samples in each acquisition cycle at correct memory locations of WFM 32. Because of the asynchronous nature of the input signal (trigger event) and the clock, such timebase correction is needed for correct representation of the signal waveform. However, since the sampling clock rate is predetermined, calculation of only a first sample of each acquisition cycle is satisfactory. Alternatively, the timebase position shaft technique of the display system as taught by U.S. Patent No. 4,251,754 to Navarro et al.

may be utilized for this purpose. It is noted that the ETD mode is usable only for repetitive input signals.

Figure 6 (B) shows the acquired samples while Figure 6 (C) shows a combined reproduced waveform on display system 46.

Figure 7 shows a circuit schematic of one example of CCD driver amplifier 20. Transistors Q1-Q2 form an input differential amplifier stage together with emitter coupling resistors R,-R2 and current source transistor 03. Transistors 04-05 and 06-a7 are two level shift stages which form a differential cascode amplifier in combination with 01-02. The voltage gain of this amplifier is approximately determined by resistors R1 through 6 Resistor R5 is variable for proper gain setting. Transistors Os-09 constitute an error correction stage that compensates for gain changes in the amplifier due to compression and signal induced thermal distortion.Transistor Q8 amplifies and inverts a portion of the (+) half of the differential signal, and adds it to the (-) half of the signal at the summing node at the emitter of transistor 07. As the (+) signal increases in amplitude, more error correction signal is added to the (-) signal, thereby creating a linear gain. Transistor Qg operates in the same manner. Resistor R7 is selected to a proper value with respect to resistors R1-R2 for the minimum distortion. Operational amplifier A1 is used to maintain a constant output voltage at the collectors of transistors 06-07.

Figure 8 is a circuit schematic of CCD output amplifier 24 and switching circuit 25 in Figure 1.

Amplifier 24a and 24b are essentially identical to each other, and only amplifier 24a is shown in detail.

Amplifier 24a comprises a pair of emitter follower amplifier stages O,,-Q,, to act as buffer stages for CCDs 22A-22B and gain controllable differential amplifier 012-012 including current source transistor 014. Potentiometer Rs is used for precise gain adjustment of the two CCDs 22A-22B. The voltage gain of differential amplifier 012-Q13 is basically determined by resistors Rlo-R11. However, a gain control circuit including a pair of FET's Q15-Q16, operational amplifiers A10-A11 and resistors R12 through R21 is used to compensate for the gains of CCDs 22A-22B. The gain control technique is similar to the one disclosed in U.S.Patent No.3,710,270. A matched FET pair Q18 and Ois thermally coupled in a single capsule act as variable resistors, while resistors R16 through R21 including FET Ole form a bridge circuit. Operational amplifier A10 compares the null voltage of the differential amplifier Q12Q13 at the node of R14-R15 with the node of R16-R17, thereby providing the output voltage of amplifier A10 to the series resistors R16 through R19 and also the series resistors R20 and R21.Amplifier A11 compares the bridge voltages at the nodes of R17-R18 and R20-R21, and provides its output to both gates of Qis-Qie The gate voltage of Q15-Q16is varied in such a manner that the bridge circuit remains balanced, thereby providing a constant source-to-drain resistance of both Q15-Q16 at a given bridge condition regardless of different temperatures. Such resistance can be varied as R19 is varied.

Switching circuit 25 comprises two pairs of common base transistors 017 through 020 connected to collectors of Q12-Q13 Of course similar transistor pairs are included in CH 2 circuit 24b. Divider resistors R22 through R25, operational amplifier A12, and diodes D1-D2 are used to maintain the emitter voltage of transistors 017 through Q20 and in turn the collector voltage of transistors 012-013 a given voltage lower than the collector voltage of current source transistors Q14. Transistors 021 through Q24 constitute a current mirror circuit for both channels.

Additional two pairs of transistors 028-026 and 027-028 and NOR gate G constitute a switch control circuit. A reference voltage is applied to the bases of transistors 026-028.

In operation, when either one or both terminals 60 and 62 is logical high, NOR gate G provides a low output, causing transitor 025 to be off and 026 to be on, thereby activating 017-018 in the CH 1. The output of CH 1 CCD 22a is now chosen and is coupled to ADC 26 for digitizing. Current mirror comprising transistors 021-024 is used for maximum use of the two push-pull (differential) outputs from the collector of transistor 018. On the other hand, when the terminal 62 is low, transistor 027 and Q26 are off and 028 and Q25 are on, thereby choosing CH 2 CCD output. The CH 1 CCD output are effectively nulled and bypassed to ground through transistors 019-020.

Figure 9 shows a more detailed block diagram of display circuitry 36 in Figure 1. This circuitry controls the display mode: Y-T (voltage Vs. time), X-Y, readout and cursor. Controlling the display cycle, blanking and reading of digital data from WFM 32 are other functions of display circuitry 36.

Mode control data latches 64 receive setup data from FP 54 through its data bus and distributes this data to various circuit blocks within this circuitry and other related circuits. Display clock 65 receives timing information from timebase 48, which is used to synchronize display circuit with memory READ X and READY time slots. It also produces a horizontal sweep rate clock which is used to digitally generate a horizontal ramp signal. Display length counter 66 counts the horizontal sweep rate clock and produces a digital horizontal ramp which is a series of digital numbers increasing sequentially from 0 to a certain number, e.g. 1024. Display control logic 67 decodes the outputs of display length counter 66 to begin and end the display cycle.X temporary latch 68 and Y temporary latch 69 receive respectively X and Y data from WFM 32 through a latched waveform data bus.

The Y data is then applied to vertical DAC 70 and blanking logic 71. The X data is applied to the X data multiplexer/latch 72 which selects either X data from WFM 32 or digital ramp data from display length counter 66 and applies its data to horizontal DAC 73.

Blanking logic 71 controls the blanking of the electron beam of the CRT. It also provides automatic blanking of the beam at the end of each display cycle and blanking between data points in the readout mode. Vector filter 74 is selectively used for displaying a continuous waveform by joining the neighbouring dots in a vector display mode. It is bypassed in a dot display mode. Display analog bus multiplexer 75 applies the mode control data of mode control data latches 64, and vertical and horizontal signals of FP 54.

Now, the operation of display circuitry 36 is discussed by reference to Figure 9. In the Y-T mode, the Y-axis data from WFM 32 in memory circuitry 30 is supplied to vertical DAC 70 by way of Y data latch 71. Display length counter 66 generates the X-axis data representing digital ramp signal which is applied via X data multiplexer/latch 72 to horizontal DAC 73. The converted Y and X analog outputs from DACs 70 and 73 are displayed as a dot at a corresponding coordinate on display system 42 either in the vector or dot mode after necessary amplification. Display length counter 66 and X data multiplexer/latch 72 are clocked at the same rate as the display address generator in memory circuitry 30, thereby displaying a series of dots at equal horizontal spacing eventually reproducing the input signal waveform on the CRT screen.

The X-Y mode is similar to the just-mentioned Y-T mode, except that X-axis waveform data from WFM 32 is substituted for the X-axis ramp data. That is, the X-axis data read from WFM 32 during a READ X time slot is latched in Xtemporary data latch 68, and, similarly, the Y-axis data read from WFM 32 during a READY time slot is latched in Y temporary data latch 69. The latched X and Y data are simultaneously applied to respective DACs 70 and 73. The X and Y data are respectively the CH 1 and CH 2 waveform data. The display cycle continues until display length counter 66 has reached its maximum count, thereby displaying a plot of one (CH 1) waveform against another (CH 2) waveform.

The readout mode is a variation of the X-Y mode.

Readout data such as characters and numbers representing stored waveforms positional order, trigger setting, delta time measurements (time difference between two cursor points on the displayed waveform) etc. are stored in WFM 32 as a series of X-Y coordinates (matrix points). Such data is then read into display circuitry 36 latched into data latches 68 and 69. They are displayed on the CRT screen during one display cycle as in the X-Y mode.

Such data is usually displayed on the upperand lower sides of the CRT screen.

The final mode (the cursor mode) is to indicate one or two cursor points on either one or both of the displayed waveforms for accurate time (delta time) measurements and is also a variation of the X-Y mode. FP 54 determines the horizontal location of the cursor on the display. Such cursor point(s) may be displayed by means of a few different techniques.

In one embodiment of the invention, FP 54 writes a waveform in WFM 32 composed only of the data points located at the cursor position. The stored waveform data is displayed in either X-Y or Y-T mode in the manner described hereinbefore. When the cursor mode is initiated, however, the stored data in FP 54 is repeatedly displayed in a time sharing manner thereby displaying the cursor dots at an intensified level (brighter than other dots).

Alternatively, the cursor position data is stored in the memory (RAM) of FP 54 to be compared by a digital comparator with the contents of horizontal display length counter 66 or data latch 68. When the two digital data coincide, the comparison output is applied to the CRT control grid to modulate its beam intensity.

The four basic modes of operation of display circuitry may now be discerned from the foregoing description. The cursor mode will be discussed hereunder more in detail.

In the Y-T waveform display mode, for example, each waveform comprises a given number of sample dots. If the sample density is 100 samples division, 1,000 sample dots make up a complete waveform. Since cursor points vary depending on the displayed waveform and the types of measurements, it is not easy to digitally locate one or more cursors on exactly the intended waveform locations in a minimum time. The technique is disclosed in U.S. Patent No. 3,843,873 to Beville et al. may be be applicable to this purpose. However, the use of a rotary control occupies a large space on the already crowded front panel. According to the cursor display of this invention, only two small push switches are used to control digital means such as a reversible counter.

Figure 10 shows a flow chart of how the counter is controlled. Cursor up and down control switches Su and Sd are used to count up or down the present count of the counter. Firstly, judgment is made if Su (or Sd) is activated. If Su (or Sd) is pushed, the counter is advanced by one step from the present count. Then, timing means measures the time duration whether or not Su (or Sd) is activated continuously over a certain iong time T1. If the activated time duration t > T1, a series of clock pulses at a first rate are applied to the counter, thereby advancing the counter at a first rate. If t > T2 (T2 > T1), the clock rate is further increased to a second rate, thereby advancing the counter at a faster rate.

Similarly, the activated time t is compared with predetermined constant values to further increase the clock rate, thereby accelerating the cursor movement until Su (or Sd) is deactivated or released when the cursor approaches the intended waveform location.

Figure 11 shows a block diagram of one embodiment of the cursor generator. Reversible counter 76 is a 10 stage (10 bits) counter to count up or down depending on the U/D control which is controlled by cursor control 77 including count up/down switches Su and Sd. Sensor 78 is used to sense if either Su or Sd is activated. Timing circuit 80 measures the activated time duration t of SulSd under control of clock generator 81. Timing circuit 80 controls the clock rate control circuit 82 which provides output pulses of different rates depending on the activation time t of SulSd. Counter 76, therefore, counts up or down at the preprogrammed acceleration fashion and the final count is stored in the predetermined memory location in the RAM (random access memory) of pRP 54 in Figure 1.For example, four memory locations in the RAM are assigned for cursor data; two cursors for each waveform.

It is to be noted that counter 76 may be replaced by an accumulator register and clock rate control circuit 82 by an incident register. The content of the latter register is controlled by P 54 depending on the activation time t and added to or subtracted from the former register depending on the activation of Su or Sd.

Figure 12 graphically shows how the cursor is moved from the present location (coordinate A) to the intended new location D. When either Su or Sd is activated at time To, the cursor advances one step and begins to move in an accelerated manner during timeT1(t1 - to = T1) until t2when switch SulSd is deactivated. The cursor location at time t2 is designated B and close to the destination D. The cursor switch is again activated for a shorter period (t2 - t3) to further advance the cursor to location C fairly close to D. SulSd is then repeatedly activated to step up/down to Dat time Tn. If the location B is close enough to D, cursor may be stopped up/down to D omitting the intermediate operation (t2 - t3). If the location C passed through the destination D, the opposite stepping direction is of course used.

Figure 13 shows examples how cursors are displayed on the waveforms. Figure 13 (A) is an example wherein both CH 1 and CH 2 waveforms include two cursors on the corresponding locations.

This mode of cursor display is called "aligned" cursor display which is particularly useful when both waveforms are time related to each other. This cursor mode is realized by reading the same cursor data for both waveforms, or by storing the same cursor data for both memory locations. In addition, the aligned cursor display is also effective for observing the CH 1 waveform alone and then observing the CH 2 waveforrn while maintaining the cursor points fixed. Figure 13 (B) is an example of an independent cursor mode wherein independent two cursors are displayed for each waveform. Of course, respective cursor data is stored in the memory.

Figure 14 shows displayed waveforms for explaining the trigger control of the digital storage oscilloscope according to this invention. The use of analog shift registers or CCDs allows the operator to select either pre-trigger, post-trigger or mixture of these trigger modes. Pre-trigger refers to a trigger mode in which the signal waveform before the triggering event is displayed. On the other hand, post-trigger refers to a trigger mode in which the signal waveform after the triggering event is displayed, which is the mode available in conventional oscilloscopes. By controlling the amount of the pre- or post-trigger mode, the triggering event may be positioned at any CRT location. However, it is very difficult and complicated to select the positioning of the waveform to be displayed on the CRT sceen.This problem may be solved by intentionally using the features of each waveform including a given number of data points per horizontal division, for example, 100 samples per division regardless of time-per-division switch settings.

The triggering event is made to be displayed at the left-most graticule line when the trigger position is set to the zero scale line, but shifts to the right by one division step as the trigger position switch is increased. For example, the trigger position will be displayed at the center of the CRT screen at trigger position 5 as shown by the solid line in Figure 14. On the contrary, the triggering event will move towards the left by one horizontal division by decreasing the trigger position even beyond the left-most graticule line in the post-trigger mode. As mentioned above, pre- or post-triggering is selected by controlling the signal acquisition timing with respect to the trigger recognition. The pre-triggering is selected if signal acquisition and writing in WFM 32 are halted upon recognition of the triggering event.On the other hand, the post-triggering mode will result if the waveform data is stored only on recognizing the triggering event. For example, if the writing of the acquired waveform data is not halted until 100 waveform data samples are stored ih WFM 32 after the triggering event in the pre-trigger mode, the triggering event will be displayed at the graticule line second from the left. Thus, the trigger position is implemented to add or subtract the digital setting by a constant number (e.g. 100) whenever the trigger position control is activated once, thereby shifting the trigger point across the entire CRT screen by only activating the switch ten times.

As is described hereinbefore, the digital storage oscilloscope according to this invention employs a pair of parallel analog shift registers per channel, ADC, digital waveform memory, display circuitry and display system. They are operated in four different modes; roll, realtime digitizing (RD), ex tended realtime digitizing (ERD) and equivalent time digitizing (ETD) depending on the timebase settings.

Waveform data is stored in the digital waveform memory at such a rate that the displayed waveform comprises a certain given number of sample data per division at any time-per-division switch setting, thereby facilitating cursor and trigger position con trol. The present invention is also incorporated with a unique accelerated cursor movement control and trigger position control. The cursor data may be independent for each channel or aligned for both channels. The cursor movement is accelerated de pending on the actuation time but is stepped by a single step for the minimum cursor adjustment time to the intended location while allowing very accurate setting. In the trigger position control, the trigger position is moved at each horizontal division and such setting is displayed numerically on the CRT screen for the operator's convenience.

Although the foregoing description is made on preferred emboidment, it should be noted that various modifications best suited for particular appli cations can be made by those having skill in the art without departing from the broad aspects of this invention. Consquently, this invention should be interpreted to include such modifications.

Claims (4)

1. In a digital storage oscilloscope including analog shift register means, an analog-to-digital converter, digital waveform memory means, a digit al-to-analog converter, and display means, the digit al storage oscilloscope characterized in the use of a pair of parallel CCDs as said analog shift register means operated in the roll, realtime digitizing, extended realtime digitizing and equivalent time digitizing modes of operation depending on time base settings.

2. In a digital storage oscilloscope according to claim 1,wherein said display means further includes a cursor generator for generating at least one cursor moving accelerated manner.

3. In a digital storage oscilloscope according to ciaim 1, wherein said display means further includes a cursor generator for generating at least one cursor for each channel of waveform, said cursors for both channels may be aligned or independently controll able.

4. A digital storage oscilloscope substantially as herein before described with reference to and as illustrated in the accompanying drawings.