GB2119607A

GB2119607A - Multi-channel display apparatus

Info

Publication number: GB2119607A
Application number: GB08305625A
Authority: GB
Inventors: Andrew Michael Oleszko
Original assignee: Lucas Industries Ltd
Current assignee: ZF International UK Ltd
Priority date: 1982-03-11
Filing date: 1983-03-01
Publication date: 1983-11-16
Also published as: GB8305625D0; GB2119607B

Abstract

A multi-channel display apparatus includes a memory circuit 15 to which digital signals are supplied from an A/D converter 14 itself supplied with analog signals from a sample and hold circuit 13. The analog signals on channel input terminals 10 are applied in turn and at a high rate to the sample and hold circuit by a multiplexer 12. The stored signals are read out of the memory circuit channel by channel and passed to a digital analogue converter 16 and the resulting analog signal supplied to a display unit 17. Offset voltages can be added to the analog signals on the channel inputs 10 before they are supplied to the sample and hold circuit, or to the analog signal supplied to the display unit. <IMAGE>

Description

SPECIFICATION Multi-channel display apparatus This invention relates to multi-channel display apparatus of the kind in which analog information applied to a number of channel input terminals is displayed in spaced relationship on a display screen.

The object of the invention is to provide such an apparatus in a simple and convenient form.

According to the invention a multi-channel display apparatus for the purpose specified comprises an analog multiplexing unit for switching the channel input terminals of the apparatus in turn to a sample and hold circuit, an analog to digital converter for converting the sampled analog signal into a digital signal, a memory circuit for storing the digital signals in turn, a digital to analog converter connected to an output terminal for converting digital signals received from the memory circuit into analog signals at said output terminal, said output terminal being connected to a deflector input of a display unit, control circuits associated with the memory circuit for ensuring that the analog signals at said input terminals are sampled in turn at a high rate and for ensuring that the stored information is read out of the memory circuit channel by channel, said control circuits including a further output terminal for connection to a trigger input of the display unit and means for introducing offset whereby the information relative to each channel is displayed in spaced relationship.

An example of an apparatus in accordance with the invention will now be described with reference to the accompanying drawings Figure 1 of which is a block diagram of the basic components of the apparatus and Figure 2 is a diagram illustrating the operation of the apparatus.

The apparatus includes a plurality of channel input terminals collectively indicated at 10 and which in use, are connected for example to a number of transducers associated with an internal combustion engine. In the particular example there are eight channel input terminals which lead to an offset unit 1 The purpose of the offset unit is to add to each channel input voltage a particular D.C. offset signal whereby the voltages applied at the input terminals will be separately displayed.

The channel output terminals of the offset unit are connected to an analog multiplexing unit 12 having a single output connected to a sample and hold circuit 13. The output of the circuit 13 is connected to an analog/digital converter 14, the output of which is connected to the write input of a memory circuit 1 5. Conveniently this is a 4K x 10 random access memory. The read output of the memory circuit 15 is applied to a digital/analog converter 16 which has an output terminal connected to the deflection input of a display unit 17 conveniently in the form of a D.C.

oscilloscope.

The operation of the memory unit is effected by a control circuit including an address multiplexer 18 and write and read address counters 19, 20 respectively. Associated with the read address counter 20 is a clock generator 21 and channel counter logic unit 22, the latter having an output which is connected to the trigger input of the display unit 1 7.

Associated with the write address counter is write control logic unit 23 which has an output connected to the sample and hold circuit 13 and the analog/digital converter 14. In addition, this output is also connected to channel control logic 24 which controls the operation of the multiplexing unit 12.

The channel control logic 24, the channel counter logic 22 and the clock generator 21 are supplied with a signal indicative of the number of channels to be displayed and the write control logic is supplied with a signal indicative of the desired sampling rate and also a start signal.

The principle of operation of the apparatus is to sample the analog signals applied to the input terminals as quickly as possible and in turn so as to build up in the memory a record of the variation of the input signals. The information is read out of the memory circuit channel by channel that is to say all the information relative to one channel is read out of the memory and displayed followed by the information relative to the next channel. In this way the time difference between the displays of the first and last channels is only the time difference between the sampling of the first channel and the sampling of the last channel.

In a particular example of the operation of the apparatus it is required to display the signals supplied to all the channel inputs and when a start signal is applied to the write control logic 23, the channel control logic 24 knowing how many channels are to be displayed, switches the multiplexing unit 12 so that the signal applied to each input 10 which has been offset, is supplied to the sample and hold circuit 13. The signal value is digitized and stored in the memory. This process is repeated for each channel input 10 and this process is arranged to occur as quickly as possible. In the particular example the process of sampling, digitizing and storing all the channels takes about 10 micro seconds. This process is repeated as often as required, the choice of the repetition rate depending upon the rate of variation of the input signals.It will be understood that when the memory circuit is full then the fresh information displaces the oldest previously stored information.

The process of reading out of the memory as stated above, takes place channel by channel and the sweep time of the oscilloscope must be at least as long and preferably slightly longer than the time required to read out all the information stored in the memory relative to one channel to ensure that all the stored information relative to each channel is displayed. In the example the read out time per channel is 2.2 milliseconds making the total read out time for eight channels 1 7.6 milliseconds. Each channel display is therefore refreshed about every 1 8 milliseconds so that the display is substantially flicker free and again in the example each channel is represented by 512 bits.

In order to improve the display, it is arranged that the digital/analog converter 1 6 includes a socalled step joining network so that the output of the converter 1 6 will be a continuous voltage as shown at 25 in Figure 2 and not a series of bits. It will be understood that because of the sweep action of the oscilloscope the channels will be displayed beiow each other on the screen. The pulses 26 in Figure 2 represent the pulses applied to the trigger input of the osciiloscope and the waveform 27 the count value of the counter 20.

If the number of channels to be displayed is reduced then the time required to digitize and store the channel information is correspondingly reduced and the amount of memory which can be allocated to each channel is increased. The practical effect of this is that the quality of the display in enhanced.

The sample rate as previously stated is selected having a knowledge of the rate of variation of the signals applied to the inputs. If the sample rate is reduced then the display is representative of the signal variation over a longer period of time.

The control logic 23 can be arranged so that the memory is updated only so far as selected channels are concerned. It will be appreciated that it is not possible to update the memory and read the contents of the memory at the same time and these two operations therefore have to be synchronized.

The offset unit 10 may incorporate variable gain amplifiers whereby the amplitudes of the traces of the signals applied at the inputs 1 0 can be separately adjusted.

Moreover, the offset unit may be positioned between the converter 16 and the display unit 17.

In this case it must also receive a control signal from the logic unit 22 to ensure that the appropriate offset voltage is applied. Furthermore, in this arrangement the amplifiers as mentioned above occupy the position of the offset unit 11 of Figure 1.

Claims

1. A multi-channel display apparatus for displaying analog information applied to a number of channel inputs, in spaced relationship on a display screen, comprising an analog multiplexing unit for switching the channel input terminals of the apparatus in turn to a sample and hold circuit, an analog to digital converter for converting the sampled analog signal into a digital signal, a memory circuit for storing the digital signals in turn, a digital to analog converter connected to an output terminal for coverting digital signals received from the memory circuit into analog signals at said output terminal, said output terminal being connected to a deflector input of a display unit, control circuits associated with the memory circuit for ensuring that the analog signals at said input terminals are sampled in turn at a high rate and for ensuring that the stored information is read out of the memory circuit channel by channel, said control circuits including a further output terminal for connection to a trigger input of the display unit and means for introducing offset whereby the information relative to each channel is displayed in spaced relationship.

2. A display apparatus according to Claim 1 including a channel offset unit located intermediate the channel inputs and said analog multiplexing unit, said offset unit acting to add to the analogue voltages applied to the channel inputs, offset voltages respectively whereby the displays on the display screen of the voltages applied to the channel inputs will be spaced.

3. A display apparatus according to Claim 1 including a channel offset unit for applying offset voltages to said analog signals at said output terminal.

4. A display apparatus according to Claim 1, Claim 2 or Claim 3 including an address multiplexer associated with the memory circuit and read and write address counters connected to the address multiplexer, a clock generator and a channel counter logic unit associated with the write address counter, said channel counter logic providing said further output terminal.

5. A display apparatus according to Claim 4 including a write control logic unit connected to said write address counter, said sample and hold circuit and said analog-digital converter, the apparatus also including a channel control logic unit which controls the operation of the analog multiplexing unit, said channel control logic unit also being connected to said write control logic unit.

6. A display apparatus according to Claim 1 including variable gain amplifiers which are connected to said channel input terminals respectively.

7. A multi-channel display apparatus for displaying analog information applied to a number of channel inputs, in spaced relationship on a display screen substantially as hereinbefore described with reference to the accompanying drawings.