GB2109210A - Signal measuring-split memory - Google Patents

Abstract

A signal measurement instrument is provided with a digital memory (36) having a plurality of separate addressable memory sectors which are addressed in a time-shared manner to permit selected sectors to be storing input signals while previously stored signals are being read out of other selected sectors. Separate address generators (32, 34) may be provided for each memory sector, with a multiplexer (38) selecting the appropriate sectors at the appropriate times. A control circuit (22) such as a microprocessor controls operation of the multiplexer, and also selects the appropriate write or read mode for each memory sector. <IMAGE>

Description

SPECIFICATION Signal measurement instrument Background of the invention The present invention relates to signal measure ment instruments which include a digital memory circuitforstoring an input signal.

A digital oscilloscope such as a transient recorder is a signal measurement instrument which converts an analog input signal to a digital signal, stores the digital signal in a digital memory circuit, and converts the stored digital signal to an analog signal for displaying on a display device such as a cathode ray tube (CRT). A logic analyzer is a signal measurement instrument which stores a digital input signal in a digital memory circuit and displays the stored digital signal on a CRT. Since these signal measurement instruments include digital memory circuits, they can acquire the input signals produced before trigger points, and, moreover, the stored digital signals can be processed by a computer. Thus, such instruments are very useful.

One conventional signal measurement instrument is the digital oscilloscope shown in Figure 1. An analog input signal at terminal 10 is converted into a digital (parallel bit) signal by analog-to-digital (A/D) converter 12, and the output signal therefrom is applied to the data input terminal of memory circuit 14, which may be a random access memory (RAM).

The digital (parallel bit) signal from the data output terminal of memory circuit 14 is converted into an analog signal by digital-to-analog (D/A) converter 16, and the output signal therefrom is applied to the vertical deflection plate of CRT 18. The address of the memory circuit 14 is determined by a parallel-bit address signal from address generator 20, which suitably may be a programmable counter, and the write and read (W/R) modes of memory circuit 14 are controlled by a control circuit 22, which may be a system consisting of a microprocessor, a read only memory (ROM) for firmwave and a RAM as a temporary memory.Control circuit 22 applies a program (preset) parallel-bit signal and a load command signal to address generator 20, and controls horizontal circuit 24 so as to generate a ramp signal to be applied to the horizontal deflection plate of CRT 18 in synchronism with the read operation of memory circuit 14. Clock generator (CLK) 26 applies a clock pulse to each block.

When control circuit 22 applies the write command signal (W) to memory circuit 14, the converter input signal is stored in memory circuit 14 in accordance with the signal from address generator 20. When memory circuit 14 receives the read command signal (R) from control circuit 22, the stored signal in memory circuit 14 is read out in accordance with the address signal, and horizontal circuit 24 generates the ramp signal in response to the command signal from control circuit 22. Since CRT 18 receives the output from D/A converter 16 as a vertical signal and the ramp signal as a horizontal signal, the input signal is displayed on CRT 18.

Control circuit 22 can preset address generator 20 for a desired address by applying an address data and the load signal to the address generator, so that the operator can observe the desired portion of the stored signal. It should be noted that a trigger circuit for determining a trigger point and a delay circuit for delaying the trigger point are eliminated from Figure 1, because these circuits are not germane to the present invention.

If control circuit 22 applies the write and read command signals alternately to memory circuit 14, the signal measurement instrument of Figure 1 can store the input signal and display the stored input signal in a time sharing manner. The displayed signal is the new input signal stored at the present time, because memory circuit 14 is both the write and read modes at the same address. However, this conventional signal measurement instrument can not acquire the new input signal while displaying the old input signal stored previously. Thus, the operator cannot use this instrument efficiently.

This disadvantage is improved by another conventional signal measurement instrument shown in Figure 2. This instrument is similar to that of Figure 1, so that the same reference numbers have been employed to designate like blocks and only the differences will be discussed. This instrument includes two memory circuits, acquisition memory circuit 28 and display memory circuit 30, and two address generators, acquisition address generator (AAG) 32 and display address generator (DAG) 34.

These memory circuits 28-30 and address generators 32-34 may be the same types mentioned in connection with Figure 1. The trigger and delay circuits are eliminated for the same reason given above for the system of Figure 1.

First, control circuit 22 causes acquisition memory circuit 28 to be in the write mode, and the output signal from AID converter 12 is stored in predetermined addresses of memory circuit 28 set by acquisition address generator 32. After the input signal is stored, control circuit 22 causes acquisition and display memory circuits 28 and 30 to be in the read and write modes respectively. The stored signal addressed by acquisition address generator 32 is applied from memory circuit 28 to memory circuit 30, and stored in memory circuit 30 in accordance with the address signal from display address generator 34. Control circuit 22 applies the read command signal to display memory circuit 30, after all of the stored signal in memory circuit 28 is transferred to memory circuit 30.The stored signal in memory circuit 30 is converted to an analog signal by D/A converter 16 and displayed on CRT 18. If the operator wants to observe the old input signal with CRT 18 while acquiring the new input signal, control circuit 22 applies the write command signal to memory circuit 28 to store the output signal from AID converter 12. Thus, the operator can observe the old input signal stored in display memory circuit 30 while acquiring the new input signal to acquisition memory circuit 28.

This conventional signal measurement instrument has a disadvantage in that the transfer time from memory circuit 28 to memory circuit 30 cannot be ignored. Desired phenomena may occur once in a while, and the occurrence time may not be known previously. In this instance, the desired phenomenon may occur during the transfer period, and the signal measurement instrument may miss a chance to acquire the phenomenon. The above described two conventional signal measurement instruments are the transient recorder type, but the logic analyzer type is in the same situation.

Summary of the invention In accordance with the present invention, a signal measurement instrument is provided with a memory partitioned into different sectors, with a separate address generator for each sector. Address signals from the respective address generators are applied to the memory sectors under control of a control circuit and a multiplexer so as to allow one memory sector to be read out while another is being written into.

It is, therefore, one object of the present invention to provide an improved signal measurement instrument which is free from the aforementioned disadvantages of the prior art.

It is another object of the present invention to provide an improved signal measurement instrument which can store a new input signal in a memory circuit and obtain a previously stored input signal from the memory circuit simultaneously at any time.

Other objects, features, and advantages of the present invention will become apparent to those skilled in the art upon a reading of the following description when taken in conjunction with the accompanying drawings.

Brief description of the drawings Figure I is a block diagram of a conventional signal measurement apparatus; Figure 2 is a block diagram of a second conventional signal measurement apparatus; Figure 3 is a block diagram of one preferred embodiment of the present invention; Figure 4 shows the memory contents of a twosector memory; and Figure 5 is a time chart for explaining the multiplexing operation.

Detailed description of the invention One preferred embodiment of the present invention will be discussed hereinafter. Figure 3 is a block diagram of the preferred embodiment. Since this embodiment includes many of the elements discussed above in connection with Figure 2, the same reference numbers have been employed to designate like blocks and only the differences will be discussed. Memory circuit 36 has at least two-timescapacity, and the memory area thereof is divided to two sectors, or first and second areas, as shown in Figure 4. Multiplexer (MUX) 38 selectively applies the address signals from acquisition and display address generators 32 and 34 to the address terminal of memory circuit 36 under control of control circuit 22. Similarly to Figures 1 and 2, the trigger and delay circuits are eliminated.

For acquiring the converted input signal from AID converter 12, control circuit 22 causes memory circuit 36 to be in the write mode and further causes multiplexer 38 to select acquisition address generator 32. Address generator 32 generates the address signal of the first area between the address numbers "0" and "m" in memory circuit 36, since control circuit 22 presets address generator 32. Thus, the output signal from AID converter 12 is stored in the first area of memory circuit 36. After the input signal is stored, control circuit 22 causes memory circuit 36 to be in the read mode, multiplexer 38 to select display address generator 34 and address generator 34 to generate the address signal of the first area in memory circuit 36.The digital output from memory circuit 36 is converted into an analog signal by D/A converter 16 and displayed on CRT 18, since horizontal circuit 24 generates the ramp signal in response to the command from control circuit 22.

To acquire a new input signal while displaying the old input signal stored in the first area of memory circuit 22, control circuit 22 applies signals A and B shown in Figure 5 to memory circuit 36 and multiplexer 38. "High" and "Low" of the control signal A instruct the read and write modes respectively.

Multiplexer 38 selects address generators 32 and 34 when the control signal B is "High" and "Low" respectively. The frequency of the signals A and B is, for example, 800 KHz. Acquisition address generator 32 generates the address signal corresponding to the second area, the address numbers from "n" to "n + m", of memory circuit 36 and display address generator 34 generates the address signal corresponding to the first area under control of control circuit 22. It should be noted that the signals A and B are synchronized with the acquisition operation of AID converter 12. First, multiplexer 38 selects address generator 34, which generates the address "0", and memory circuit 36 is in the read mode, so that the old input signal stored in the address "0" of memory circuit 36 is read out.Second, multiplexer 38 selects address generator 32, which generates the address "n" and memory circuit 36 is in the write mode, thereby storing the new input signal in the address "n" of memory circuit 36. Third, multiplexer 38 selects address generator 34, which generates the address "1" and the read mode is selected, thereby reading the signal stored in the address "1" of memory circuit 36. These operations are continued in sequence until address generators 32 and 34 generate the addresses "n + m" and "m" respectively, and the address-generating cycle returns to "n" and "0". The above time-sharing operation cycle is repeated. The phase of the signal A is later than that of the signal B because of the characteristics of memory circuit 36. Since the old input signal stored in the first area of memory circuit 36 is not transferred, there is no dead time, and the new input signal can be acquired immediately after the old input signal is acquired. Thus, the present invention can avoid missing the chance to acquire the phenomenon.

To acquire the next new input signal, acquisition address generator 32 generates the address signal corresponding to the first area of memory circuit 36 and display address generator 34 generates the address signal corresponding to the second area.

Thus, the next new input signal is stored in the first area and the signal stored in the second area is read out from memory circuit 36 in the time-sharing manner.

The embodiment of Figure 3 is a transient recorder, but it can be applied to a logic analyzer by removing AID converter 12 and D/A converter 16.

The output from memory circuit 36 may be applied to a computer for processing.

As understood from the above description, the signal measurement instrument of the present invention can store a new input signal in a memory circuit and obtain a previously stored input signal from the memory circuit simultaneously at any time.

Although the above description was made only on one preferred embodiment of the present invention, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the present invention. For example, the memory area of the memory circuit may be divided to four for acquiring two channel input signals. In this instance, two input signals may be applied alternately to the memory circuit, and the acquisition and display address generators may generate two address signals respectively for the two channel signals. The two channel input signals may be stored alternately in the sequential memory addresses of the memory circuit. Additional acquisition and display address generators may be provided, and the multiplexer selects one of four address generators. The memory circuit may be a dynamic RAM and the address generators may generate the column and row address signals. The memory circuit may store other data such as trigger and cursor information in additional memory areas. For this object, a multiplexer may be provided to selectively apply the input signal and the other information to the data input terminal of the memory circuit.

Claims (2)

1. A signal measurement instrument, comprising: a digital memory having a plurality of addressable memory sectors; a plurality of address signals generators, each corresponding to a respective memory sector; a multiplexer for selectively applying said plurality of address signals to said plurality of memory sectors; and control means for controlling the selection operation of said multiplexer, said control means also selectively controlling the write and read modes of said memory sectors in such a manner that one or more input signals may be stored in selected memory sectors while previously stored signals may be read out of other selected memory sectors.

2. A signal measurement instrument substantially as hereinbefore described with reference to Figures 3 to 5 of the accompanying drawings.