FR2496315A1 - Systeme de memoire tampon - Google Patents

Systeme de memoire tampon Download PDF

Info

Publication number
FR2496315A1
FR2496315A1 FR8123302A FR8123302A FR2496315A1 FR 2496315 A1 FR2496315 A1 FR 2496315A1 FR 8123302 A FR8123302 A FR 8123302A FR 8123302 A FR8123302 A FR 8123302A FR 2496315 A1 FR2496315 A1 FR 2496315A1
Authority
FR
France
Prior art keywords
address
address signal
physical
general
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8123302A
Other languages
English (en)
French (fr)
Other versions
FR2496315B1 (enExample
Inventor
Masanobu Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP55176974A external-priority patent/JPS57100682A/ja
Priority claimed from JP1981001939U external-priority patent/JPS57114749U/ja
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2496315A1 publication Critical patent/FR2496315A1/fr
Application granted granted Critical
Publication of FR2496315B1 publication Critical patent/FR2496315B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR8123302A 1980-12-15 1981-12-14 Systeme de memoire tampon Granted FR2496315A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP55176974A JPS57100682A (en) 1980-12-15 1980-12-15 Address buffer memory system
JP1981001939U JPS57114749U (enExample) 1981-01-09 1981-01-09

Publications (2)

Publication Number Publication Date
FR2496315A1 true FR2496315A1 (fr) 1982-06-18
FR2496315B1 FR2496315B1 (enExample) 1985-01-18

Family

ID=26335235

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8123302A Granted FR2496315A1 (fr) 1980-12-15 1981-12-14 Systeme de memoire tampon

Country Status (2)

Country Link
US (1) US4482952A (enExample)
FR (1) FR2496315A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3833933A1 (de) * 1987-10-05 1989-04-20 Hitachi Ltd Informationsverarbeitungseinrichtung mit einer adressenerweiterungsfunktion
EP0339157A3 (en) * 1988-04-26 1990-09-05 Ing. C. Olivetti & C., S.p.A. Address translating apparatus for a computer memory

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523275A (en) * 1980-11-14 1985-06-11 Sperry Corporation Cache/disk subsystem with floating entry
US4574351A (en) * 1983-03-03 1986-03-04 International Business Machines Corporation Apparatus for compressing and buffering data
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4654790A (en) * 1983-11-28 1987-03-31 Amdahl Corporation Translation of virtual and real addresses to system addresses
GB8405491D0 (en) * 1984-03-02 1984-04-04 Hemdal G Computers
JPH0652511B2 (ja) * 1984-12-14 1994-07-06 株式会社日立製作所 情報処理装置のアドレス変換方式
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US5237671A (en) * 1986-05-02 1993-08-17 Silicon Graphics, Inc. Translation lookaside buffer shutdown scheme
US5146606A (en) * 1986-09-18 1992-09-08 Digital Equipment Corporation Systems for interconnecting and configuring plurality of memory elements by control of mode signals
US5230079A (en) * 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5239635A (en) * 1988-06-06 1993-08-24 Digital Equipment Corporation Virtual address to physical address translation using page tables in virtual memory
US7447069B1 (en) 1989-04-13 2008-11-04 Sandisk Corporation Flash EEprom system
EP0935255A2 (en) 1989-04-13 1999-08-11 SanDisk Corporation Flash EEPROM system
US7190617B1 (en) * 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
US5278961A (en) * 1990-02-22 1994-01-11 Hewlett-Packard Company Physical address to logical address translator for memory management units
US5771368A (en) * 1990-10-29 1998-06-23 Sun Microsystems, Inc. Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers
JPH11144496A (ja) * 1997-11-10 1999-05-28 Nec Corp Ｌｓｉセル位置情報出力装置、出力方法およびｌｓｉセル位置情報出力プログラムの記録媒体
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6807615B1 (en) * 1999-04-08 2004-10-19 Sun Microsystems, Inc. Apparatus and method for providing a cyclic buffer using logical blocks
US20040088474A1 (en) * 2002-10-30 2004-05-06 Lin Jin Shin NAND type flash memory disk device and method for detecting the logical address

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US3761881A (en) * 1971-06-30 1973-09-25 Ibm Translation storage scheme for virtual memory system
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR130806A (enExample) * 1973-11-21
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
US4130867A (en) * 1975-06-19 1978-12-19 Honeywell Information Systems Inc. Database instruction apparatus for determining a database record type
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
US4373179A (en) * 1978-06-26 1983-02-08 Fujitsu Limited Dynamic address translation system
US4218743A (en) * 1978-07-17 1980-08-19 International Business Machines Corporation Address translation apparatus
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
US4400700A (en) * 1981-06-08 1983-08-23 The United States Of America As Represented By The Secretary Of The Army Doppler frequency analysis of radar signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761881A (en) * 1971-06-30 1973-09-25 Ibm Translation storage scheme for virtual memory system
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3833933A1 (de) * 1987-10-05 1989-04-20 Hitachi Ltd Informationsverarbeitungseinrichtung mit einer adressenerweiterungsfunktion
EP0339157A3 (en) * 1988-04-26 1990-09-05 Ing. C. Olivetti & C., S.p.A. Address translating apparatus for a computer memory

Also Published As

Publication number Publication date
FR2496315B1 (enExample) 1985-01-18
US4482952A (en) 1984-11-13

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