FR2481005B1 - - Google Patents

Info

Publication number
FR2481005B1
FR2481005B1 FR8107374A FR8107374A FR2481005B1 FR 2481005 B1 FR2481005 B1 FR 2481005B1 FR 8107374 A FR8107374 A FR 8107374A FR 8107374 A FR8107374 A FR 8107374A FR 2481005 B1 FR2481005 B1 FR 2481005B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8107374A
Other languages
French (fr)
Other versions
FR2481005A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/141,120 external-priority patent/US4343082A/en
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of FR2481005A1 publication Critical patent/FR2481005A1/fr
Application granted granted Critical
Publication of FR2481005B1 publication Critical patent/FR2481005B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
FR8107374A 1980-04-17 1981-04-13 Procede de fabrication de transistors a effet de champ a canal court Granted FR2481005A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14112180A 1980-04-17 1980-04-17
US06/141,120 US4343082A (en) 1980-04-17 1980-04-17 Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device

Publications (2)

Publication Number Publication Date
FR2481005A1 FR2481005A1 (fr) 1981-10-23
FR2481005B1 true FR2481005B1 (OSRAM) 1983-10-21

Family

ID=26838805

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8107374A Granted FR2481005A1 (fr) 1980-04-17 1981-04-13 Procede de fabrication de transistors a effet de champ a canal court

Country Status (5)

Country Link
DE (1) DE3115596A1 (OSRAM)
FR (1) FR2481005A1 (OSRAM)
GB (1) GB2074374B (OSRAM)
IT (1) IT1135748B (OSRAM)
NL (1) NL8101902A (OSRAM)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1197926A (en) * 1981-12-16 1985-12-10 William D. Ryden Zero drain overlap and self-aligned contacts and contact methods for mod devices
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen
FR2525029A1 (fr) * 1982-04-08 1983-10-14 Commissariat Energie Atomique Procede d'isolation d'une ligne conductrice dans un circuit integre et procede de fabrication d'un transistor mos utilisant un tel procede d'isolation
US4485550A (en) * 1982-07-23 1984-12-04 At&T Bell Laboratories Fabrication of schottky-barrier MOS FETs
JPS59106172A (ja) * 1982-12-07 1984-06-19 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 電界効果トランジスタの製造方法
JPS59210642A (ja) * 1983-05-16 1984-11-29 Hitachi Ltd 半導体装置の製造方法
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS

Also Published As

Publication number Publication date
DE3115596A1 (de) 1982-04-01
GB2074374B (en) 1984-04-26
DE3115596C2 (OSRAM) 1988-04-14
NL8101902A (nl) 1981-11-16
FR2481005A1 (fr) 1981-10-23
IT8121239A0 (it) 1981-04-16
GB2074374A (en) 1981-10-28
IT1135748B (it) 1986-08-27

Similar Documents

Publication Publication Date Title
FR2484344B1 (OSRAM)
FR2488680B1 (OSRAM)
FR2492221B3 (OSRAM)
GR74687B (OSRAM)
FR2483941B1 (OSRAM)
GR74896B (OSRAM)
FR2478682B1 (OSRAM)
FR2488645B2 (OSRAM)
JPS56102046U (OSRAM)
FR2482211B1 (OSRAM)
IN157830B (OSRAM)
FR2473995B1 (OSRAM)
FR2475376B1 (OSRAM)
FR2482646B1 (OSRAM)
FR2485003B1 (OSRAM)
FR2486392B1 (OSRAM)
FR2511690B1 (OSRAM)
FR2476474B1 (OSRAM)
GR73020B (OSRAM)
JPS56104590U (OSRAM)
FR2493116B3 (OSRAM)
FR2473006B3 (OSRAM)
JPS56104312U (OSRAM)
JPS56106466U (OSRAM)
JPS56104675U (OSRAM)

Legal Events

Date Code Title Description
ST Notification of lapse