FR2456367A1 - Dispositif de memorisation d'information perfectionne - Google Patents

Dispositif de memorisation d'information perfectionne

Info

Publication number
FR2456367A1
FR2456367A1 FR8010495A FR8010495A FR2456367A1 FR 2456367 A1 FR2456367 A1 FR 2456367A1 FR 8010495 A FR8010495 A FR 8010495A FR 8010495 A FR8010495 A FR 8010495A FR 2456367 A1 FR2456367 A1 FR 2456367A1
Authority
FR
France
Prior art keywords
memory device
information memory
repositioned
write operations
improved information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8010495A
Other languages
English (en)
Other versions
FR2456367B1 (fr
Inventor
Philip Broughton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of FR2456367A1 publication Critical patent/FR2456367A1/fr
Application granted granted Critical
Publication of FR2456367B1 publication Critical patent/FR2456367B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

L'INVENTION CONCERNE UN DISPOSITIF DE MEMORISATION D'INFORMATION. IL COMPREND DEUX MEMOIRES A ACCES DIRECTM1, M2. LORSQU'UNE MEMOIRE EST EN COURS D'UTILISATION POUR DES OPERATIONS NORMALES DE LECTURE-ECRITURE, L'AUTRE EST AUTOMATIQUEMENT ATTAQUEE DE FACON QUE CHAQUE EMPLACEMENT PUISSE ETRE REPOSITIONNE. LORSQU'UN ORDRE DE REPOSITIONNEMENT EST RECU, IL EST EFFECTUE UN ECHANGE DES ROLES DES DEUX MEMOIRES, SI BIEN QUE CELLE QUI VIENT D'ETRE REPOSITIONNEE EST ALORS SOUMISE AUX OPERATIONS NORMALES DE LECTURE-ECRITURE. CECI PERMET D'EFFECTUER DES REPOSITIONNEMENTS TRES RAPIDEMENT. L'INVENTION S'APPLIQUE PARTICULIEREMENT A LA MEMORISATION DE BITS DE REPERES DE VALIDITE RELATIFS A DES ARTICLES DE DONNEES D'UNE MEMOIRE ASSERVIE.
FR8010495A 1979-05-09 1980-05-09 Dispositif de memorisation d'information perfectionne Expired FR2456367B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7916020 1979-05-09

Publications (2)

Publication Number Publication Date
FR2456367A1 true FR2456367A1 (fr) 1980-12-05
FR2456367B1 FR2456367B1 (fr) 1986-07-25

Family

ID=10505029

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8010495A Expired FR2456367B1 (fr) 1979-05-09 1980-05-09 Dispositif de memorisation d'information perfectionne

Country Status (6)

Country Link
US (1) US4310902A (fr)
AU (1) AU539369B2 (fr)
BE (1) BE884825A (fr)
DE (1) DE3016269A1 (fr)
FR (1) FR2456367B1 (fr)
ZA (1) ZA802367B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787032B2 (ja) * 1985-07-08 1995-09-20 日本電気アイシ−マイコンシステム株式会社 半導体記憶装置
US5076480A (en) * 1990-09-27 1991-12-31 Dennison Manufacturing Company Variable pitch feed of fasteners
US20040064657A1 (en) * 2002-09-27 2004-04-01 Muraleedhara Navada Memory structure including information storage elements and associated validity storage elements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4008460A (en) * 1975-12-24 1977-02-15 International Business Machines Corporation Circuit for implementing a modified LRU replacement algorithm for a cache
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
US3675218A (en) * 1970-01-15 1972-07-04 Ibm Independent read-write monolithic memory array
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory
GB1487706A (en) * 1976-01-16 1977-10-05 Plessey Co Ltd Data storage arrangement for buffering asynchronous input and output data streams

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4008460A (en) * 1975-12-24 1977-02-15 International Business Machines Corporation Circuit for implementing a modified LRU replacement algorithm for a cache
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 13, no. 2, juillet 1970, New York (US) *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 13, no. 9, février 1971, New York (US) *

Also Published As

Publication number Publication date
BE884825A (fr) 1981-02-19
AU5821980A (en) 1980-11-13
DE3016269A1 (de) 1980-11-20
ZA802367B (en) 1981-04-29
FR2456367B1 (fr) 1986-07-25
US4310902A (en) 1982-01-12
DE3016269C2 (fr) 1988-09-08
AU539369B2 (en) 1984-09-27

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Legal Events

Date Code Title Description
ST Notification of lapse