FR2420792A1 - Circuit multiplicateur-accumulateur - Google Patents

Circuit multiplicateur-accumulateur

Info

Publication number
FR2420792A1
FR2420792A1 FR7905941A FR7905941A FR2420792A1 FR 2420792 A1 FR2420792 A1 FR 2420792A1 FR 7905941 A FR7905941 A FR 7905941A FR 7905941 A FR7905941 A FR 7905941A FR 2420792 A1 FR2420792 A1 FR 2420792A1
Authority
FR
France
Prior art keywords
multiplier
circuit
accumulator
accumulator circuit
accumulator register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7905941A
Other languages
English (en)
Other versions
FR2420792B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Space and Mission Systems Corp
Original Assignee
TRW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Publication of FR2420792A1 publication Critical patent/FR2420792A1/fr
Application granted granted Critical
Publication of FR2420792B1 publication Critical patent/FR2420792B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)

Abstract

Un circuit multiplicateur-accumulateur comporte notamment un circuit multiplicateur 14 dont les signaux de sortie sont chargés sélectivement dans un registre accumulateur 18 sous la commande d'un circuit logique de commande de pré-chargement 40. Le circuit 40 permet de pré-charger dans le registre accumulateur des données externes, appliquées sur les bornes 46a-46c, qui correspondent par exemple à un résultat intermédiaire antérieur. Application aux ordinateurs.
FR7905941A 1978-03-22 1979-03-08 Circuit multiplicateur-accumulateur Granted FR2420792A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/888,980 US4215416A (en) 1978-03-22 1978-03-22 Integrated multiplier-accumulator circuit with preloadable accumulator register

Publications (2)

Publication Number Publication Date
FR2420792A1 true FR2420792A1 (fr) 1979-10-19
FR2420792B1 FR2420792B1 (fr) 1984-01-13

Family

ID=25394295

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7905941A Granted FR2420792A1 (fr) 1978-03-22 1979-03-08 Circuit multiplicateur-accumulateur

Country Status (6)

Country Link
US (1) US4215416A (fr)
JP (1) JPS54128233A (fr)
DE (1) DE2911096A1 (fr)
FR (1) FR2420792A1 (fr)
GB (1) GB2015784B (fr)
SE (1) SE436666B (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559608A (en) * 1983-01-21 1985-12-17 Harris Corporation Arithmetic logic unit
FR2544104B1 (fr) * 1983-04-06 1985-06-14 Thomson Csf Integrateur modulaire
US4597053A (en) * 1983-07-01 1986-06-24 Codex Corporation Two-pass multiplier/accumulator circuit
WO1986002181A1 (fr) * 1984-09-28 1986-04-10 Motorola, Inc. Processeur de signaux numeriques pour miltiplication/accumulation en un seul cycle
JPS6182234A (ja) * 1984-09-29 1986-04-25 Toshiba Corp 乗算器回路
US4692888A (en) * 1984-10-03 1987-09-08 Advanced Micro Devices, Inc. Method and apparatus for generating and summing the products of pairs of numbers
JPS6263370A (ja) * 1985-05-15 1987-03-20 Toshiba Corp 演算回路
US4748580A (en) * 1985-08-30 1988-05-31 Advanced Micro Devices, Inc. Multi-precision fixed/floating-point processor
US4754421A (en) * 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device
GB8612453D0 (en) * 1986-05-22 1986-07-02 Inmos Ltd Multistage digital signal multiplication & addition
US4831577A (en) * 1986-09-17 1989-05-16 Intersil, Inc. Digital multiplier architecture with triple array summation of partial products
US4802091A (en) * 1986-10-31 1989-01-31 International Business Machines Corporation Method for improving the efficiency of arithmetic code generation in an optimizing compiler using the technique of reassociation
US4876660A (en) * 1987-03-20 1989-10-24 Bipolar Integrated Technology, Inc. Fixed-point multiplier-accumulator architecture
JP3053092B2 (ja) * 1987-06-05 2000-06-19 株式会社日立製作所 並列化コンパイル方法
US4958312A (en) * 1987-11-09 1990-09-18 Lsi Logic Corporation Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults
JP2964172B2 (ja) * 1991-03-08 1999-10-18 富士通株式会社 Ｄｃｔマトリクス演算回路
US5241492A (en) * 1991-05-06 1993-08-31 Motorola, Inc. Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor
JPH05216624A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 演算装置
US5958001A (en) * 1994-03-31 1999-09-28 Motorola, Inc. Output-processing circuit for a neural network and method of using same
US6247036B1 (en) * 1996-01-22 2001-06-12 Infinite Technology Corp. Processor with reconfigurable arithmetic data path
KR100287894B1 (ko) * 1998-03-05 2001-05-02 김영환 콤필터의미분기
TW407770U (en) * 1998-09-18 2000-10-01 Ind Tech Res Inst 50MHz 40-bit accumulator with trigger capability

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2127343A5 (fr) * 1971-02-25 1972-10-13 Ibm France
US3840861A (en) * 1972-10-30 1974-10-08 Amdahl Corp Data processing system having an instruction pipeline for concurrently processing a plurality of instructions
FR2308144A1 (fr) * 1975-04-18 1976-11-12 Ibm France Dispositif generateur de fonction de convolution discrete et filtre numerique incorporant ledit dispositif

Also Published As

Publication number Publication date
JPS54128233A (en) 1979-10-04
GB2015784B (en) 1982-03-10
DE2911096C2 (fr) 1988-05-05
GB2015784A (en) 1979-09-12
DE2911096A1 (de) 1979-10-04
US4215416A (en) 1980-07-29
SE436666B (sv) 1985-01-14
SE7902520L (sv) 1979-09-23
JPS6135590B2 (fr) 1986-08-13
FR2420792B1 (fr) 1984-01-13

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Legal Events

Date Code Title Description
ST Notification of lapse