FR2420253A1 - Asservissement a boucle de phase numerique programmable - Google Patents

Asservissement a boucle de phase numerique programmable

Info

Publication number
FR2420253A1
FR2420253A1 FR7807760A FR7807760A FR2420253A1 FR 2420253 A1 FR2420253 A1 FR 2420253A1 FR 7807760 A FR7807760 A FR 7807760A FR 7807760 A FR7807760 A FR 7807760A FR 2420253 A1 FR2420253 A1 FR 2420253A1
Authority
FR
France
Prior art keywords
clock source
binary counter
phase control
transceivers
digital phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7807760A
Other languages
English (en)
Other versions
FR2420253B1 (fr
Inventor
Edouard Marie Jean A Issenmann
Marc Louis Francois Gineston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Le Materiel Telephonique Thomson CSF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Le Materiel Telephonique Thomson CSF filed Critical Le Materiel Telephonique Thomson CSF
Priority to FR7807760A priority Critical patent/FR2420253A1/fr
Publication of FR2420253A1 publication Critical patent/FR2420253A1/fr
Application granted granted Critical
Publication of FR2420253B1 publication Critical patent/FR2420253B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

L'invention concerne un asservissement de phase numérique programmable pour récepteur de transmission de données. Cet asservissement comporte un détecteur de fronts et une boucle de phase programmable, constituée par un compteur à n étages et une mémoire. L'invention est utilisable notamment pour synchroniser une horloge.
FR7807760A 1978-03-17 1978-03-17 Asservissement a boucle de phase numerique programmable Granted FR2420253A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7807760A FR2420253A1 (fr) 1978-03-17 1978-03-17 Asservissement a boucle de phase numerique programmable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7807760A FR2420253A1 (fr) 1978-03-17 1978-03-17 Asservissement a boucle de phase numerique programmable

Publications (2)

Publication Number Publication Date
FR2420253A1 true FR2420253A1 (fr) 1979-10-12
FR2420253B1 FR2420253B1 (fr) 1983-01-21

Family

ID=9205935

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7807760A Granted FR2420253A1 (fr) 1978-03-17 1978-03-17 Asservissement a boucle de phase numerique programmable

Country Status (1)

Country Link
FR (1) FR2420253A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2481030A1 (fr) * 1980-04-22 1981-10-23 Sony Corp Circuit de reproduction d'un signal de cadence de bits
FR2498035A1 (fr) * 1981-01-09 1982-07-16 Thomson Csf Procede et dispositif de synchronisation de messages
FR2579042A1 (fr) * 1985-03-18 1986-09-19 Bull Micral Procede d'extraction d'un signal d'horloge synchrone a partir d'un signal code en simple ou double intensite, et dispositif permettant la mise en oeuvre du procede
USRE36803E (en) * 1980-04-22 2000-08-01 Sony Corporation Bit clock reproducing circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671873A (en) * 1970-03-23 1972-06-20 Siemens Ag Circuit arrangement for generation timing pulses
DE2613930A1 (de) * 1976-03-31 1977-10-06 Siemens Ag Digitaler phasenregelkreis

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671873A (en) * 1970-03-23 1972-06-20 Siemens Ag Circuit arrangement for generation timing pulses
DE2613930A1 (de) * 1976-03-31 1977-10-06 Siemens Ag Digitaler phasenregelkreis

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2481030A1 (fr) * 1980-04-22 1981-10-23 Sony Corp Circuit de reproduction d'un signal de cadence de bits
USRE36803E (en) * 1980-04-22 2000-08-01 Sony Corporation Bit clock reproducing circuit
FR2498035A1 (fr) * 1981-01-09 1982-07-16 Thomson Csf Procede et dispositif de synchronisation de messages
EP0056208A1 (fr) * 1981-01-09 1982-07-21 Thomson-Csf Procédé et dispositif de synchronisation de messages
FR2579042A1 (fr) * 1985-03-18 1986-09-19 Bull Micral Procede d'extraction d'un signal d'horloge synchrone a partir d'un signal code en simple ou double intensite, et dispositif permettant la mise en oeuvre du procede
EP0196255A1 (fr) * 1985-03-18 1986-10-01 Bull S.A. Procédé d'extraction d'un signal d'horloge synchrone à partir d'un signal codé en simple ou double densité, et dispositif permettant la mise en oeuvre du procédé
US4809304A (en) * 1985-03-18 1989-02-28 Bull, S. A. Method of extracting a synchronous clock signal from a single- or double-density coded signal, and apparatus for performing the method

Also Published As

Publication number Publication date
FR2420253B1 (fr) 1983-01-21

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Legal Events

Date Code Title Description
ST Notification of lapse