FR2415392B1 - - Google Patents

Info

Publication number
FR2415392B1
FR2415392B1 FR7801600A FR7801600A FR2415392B1 FR 2415392 B1 FR2415392 B1 FR 2415392B1 FR 7801600 A FR7801600 A FR 7801600A FR 7801600 A FR7801600 A FR 7801600A FR 2415392 B1 FR2415392 B1 FR 2415392B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7801600A
Other versions
FR2415392A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bpifrance Financement SA
Original Assignee
Agence National de Valorisation de la Recherche ANVAR
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agence National de Valorisation de la Recherche ANVAR filed Critical Agence National de Valorisation de la Recherche ANVAR
Priority to FR7801600A priority Critical patent/FR2415392A1/fr
Priority to GB7901263A priority patent/GB2015289B/en
Priority to NL7900398A priority patent/NL7900398A/xx
Priority to JP404379A priority patent/JPS54113283A/ja
Priority to DE19792902112 priority patent/DE2902112A1/de
Publication of FR2415392A1 publication Critical patent/FR2415392A1/fr
Application granted granted Critical
Publication of FR2415392B1 publication Critical patent/FR2415392B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06GANALOGUE COMPUTERS
    • G06G7/00Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34DC amplifiers in which all stages are DC-coupled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1735Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/04Position modulation, i.e. PPM
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/06Frequency or rate modulation, i.e. PFM or PRM

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Software Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Amplitude Modulation (AREA)
FR7801600A 1978-01-20 1978-01-20 Circuit electronique multifonction a quatre circuits de base et applications de ce circuit Granted FR2415392A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR7801600A FR2415392A1 (fr) 1978-01-20 1978-01-20 Circuit electronique multifonction a quatre circuits de base et applications de ce circuit
GB7901263A GB2015289B (en) 1978-01-20 1979-01-12 Multifunction electronic circuit arrangement having four basic circuits and applications of said circuit arrangement
NL7900398A NL7900398A (nl) 1978-01-20 1979-01-18 Elektronische multi-funktieschakeling.
JP404379A JPS54113283A (en) 1978-01-20 1979-01-19 Multiifunction circuit
DE19792902112 DE2902112A1 (de) 1978-01-20 1979-01-19 Elektronische mehrfunktions-schaltungsanordnung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7801600A FR2415392A1 (fr) 1978-01-20 1978-01-20 Circuit electronique multifonction a quatre circuits de base et applications de ce circuit

Publications (2)

Publication Number Publication Date
FR2415392A1 FR2415392A1 (fr) 1979-08-17
FR2415392B1 true FR2415392B1 (fr) 1980-06-06

Family

ID=9203682

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7801600A Granted FR2415392A1 (fr) 1978-01-20 1978-01-20 Circuit electronique multifonction a quatre circuits de base et applications de ce circuit

Country Status (5)

Country Link
JP (1) JPS54113283A (fr)
DE (1) DE2902112A1 (fr)
FR (1) FR2415392A1 (fr)
GB (1) GB2015289B (fr)
NL (1) NL7900398A (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3133518A1 (de) * 1981-08-25 1983-03-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt "elektronischer schalter"
JPH0669142B2 (ja) * 1983-04-15 1994-08-31 株式会社日立製作所 半導体集積回路装置
GB2161044B (en) * 1984-06-28 1988-01-27 Stc Plc Telephone subscribers circuits
JPS61186019A (ja) * 1985-02-13 1986-08-19 Toshiba Corp E↑2prom
GB2228154B (en) * 1989-02-09 1993-04-21 Plessey Co Plc On-chip integrated oscillator circuits
JP2622051B2 (ja) * 1992-06-19 1997-06-18 株式会社東芝 Eeprom
US6803832B2 (en) * 2002-09-06 2004-10-12 Freescale Semiconductor, Inc. Oscillator circuit having reduced layout area and lower power supply transients

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3694931A (en) * 1970-01-06 1972-10-03 Joseph J Bialek Training device for teaching digital logic operations

Also Published As

Publication number Publication date
JPS54113283A (en) 1979-09-04
DE2902112A1 (de) 1979-09-06
FR2415392A1 (fr) 1979-08-17
NL7900398A (nl) 1979-07-24
GB2015289A (en) 1979-09-05
GB2015289B (en) 1982-08-18

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Legal Events

Date Code Title Description
ST Notification of lapse