FR2396453A1 - Horloge centrale - Google Patents

Horloge centrale

Info

Publication number
FR2396453A1
FR2396453A1 FR7819446A FR7819446A FR2396453A1 FR 2396453 A1 FR2396453 A1 FR 2396453A1 FR 7819446 A FR7819446 A FR 7819446A FR 7819446 A FR7819446 A FR 7819446A FR 2396453 A1 FR2396453 A1 FR 2396453A1
Authority
FR
France
Prior art keywords
input
loops
control
phase
plli
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7819446A
Other languages
English (en)
Inventor
Frans Andre Jozef Haerens
Michel Louis Maria Smouts
Willy Louis Verreycken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of FR2396453A1 publication Critical patent/FR2396453A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0005—Transmission of control signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Horloge centrale à au moins deux boucles d'asservissement de phase dont les signaux de sortie sont sélectionnés par décision majoritaire. Un seule maître oscillateur MO est utilisé avec, par exemple, trois boucles PLLI-3 à comparateur numérique de phase entre la sortie f et l'entrée F et oscillateur commandé en tension OCT en fonction de l'erreur de phase. L'entrée F est appliquée via des circuits de logique IGC qui, sous le contrôle de circuits de décision MDC commandés par des détecteurs d'état des boucles (verrouillage de phase ou non), sélectionnent pour la boucle PLL2 le signal de sortie fl de PLLI ou celui du maître oscillateur f et, pour PLL3, le signal de sortie de PLL1 f1 ou de PLL2 f2. En l'absence d'entrée F, un commutateur FCC ouvre la boucle de façon que l'OCT fonctionne indépendamment à une fréquence définie. Application particulière aux circuits de commande de systèmes de commutation électronique.
FR7819446A 1977-06-30 1978-06-29 Horloge centrale Withdrawn FR2396453A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7707260A NL7707260A (nl) 1977-06-30 1977-06-30 Moederklokinrichting.

Publications (1)

Publication Number Publication Date
FR2396453A1 true FR2396453A1 (fr) 1979-01-26

Family

ID=19828807

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7819446A Withdrawn FR2396453A1 (fr) 1977-06-30 1978-06-29 Horloge centrale

Country Status (8)

Country Link
AU (1) AU3727178A (fr)
BE (1) BE868559R (fr)
BR (1) BR7804221A (fr)
DE (1) DE2828300A1 (fr)
ES (1) ES471307A1 (fr)
FR (1) FR2396453A1 (fr)
GB (1) GB2000651B (fr)
NL (1) NL7707260A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3241189A1 (de) * 1982-11-08 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Taktstromversorgung fuer ein multimikrocomputersystem in eisenbahnsicherungsanlagen
JPH0797328B2 (ja) * 1988-10-25 1995-10-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン フオールト・トレラント同期システム
US5469467A (en) * 1993-10-15 1995-11-21 At&T Corp. Method for synchronizing the reference frequency oscillator of a metallic-based microcell to a master oscillator
US6188286B1 (en) * 1999-03-30 2001-02-13 Infineon Technologies North America Corp. Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1548995A (fr) * 1966-12-21 1968-12-06
GB1159887A (en) * 1966-12-09 1969-07-30 Varian Associates Sequential Frequency Combiner for Frequency Standard Systems
GB1238582A (fr) * 1969-08-15 1971-07-07
GB1253309A (en) * 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
GB1263276A (en) * 1969-04-14 1972-02-09 Marconi Co Ltd Improvements in or relating to clock oscillator arrangements
FR2315736A1 (fr) * 1975-06-25 1977-01-21 Materiel Telephonique Systeme de transmission de signaux periodiques

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1159887A (en) * 1966-12-09 1969-07-30 Varian Associates Sequential Frequency Combiner for Frequency Standard Systems
FR1548995A (fr) * 1966-12-21 1968-12-06
GB1263276A (en) * 1969-04-14 1972-02-09 Marconi Co Ltd Improvements in or relating to clock oscillator arrangements
GB1238582A (fr) * 1969-08-15 1971-07-07
GB1253309A (en) * 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
FR2315736A1 (fr) * 1975-06-25 1977-01-21 Materiel Telephonique Systeme de transmission de signaux periodiques

Also Published As

Publication number Publication date
GB2000651A (en) 1979-01-10
BE868559R (nl) 1978-12-29
BR7804221A (pt) 1979-05-15
AU3727178A (en) 1980-01-03
DE2828300A1 (de) 1979-01-11
NL7707260A (nl) 1979-01-03
GB2000651B (en) 1982-05-06
ES471307A1 (es) 1979-01-16

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Legal Events

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