FR2389173A1 - Additionneur a sauvegarde des retenues - Google Patents

Additionneur a sauvegarde des retenues

Info

Publication number
FR2389173A1
FR2389173A1 FR7809188A FR7809188A FR2389173A1 FR 2389173 A1 FR2389173 A1 FR 2389173A1 FR 7809188 A FR7809188 A FR 7809188A FR 7809188 A FR7809188 A FR 7809188A FR 2389173 A1 FR2389173 A1 FR 2389173A1
Authority
FR
France
Prior art keywords
carry
sum
adder
triggered
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7809188A
Other languages
English (en)
Other versions
FR2389173B1 (fr
Inventor
Joel C Leininger
George P Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2389173A1 publication Critical patent/FR2389173A1/fr
Application granted granted Critical
Publication of FR2389173B1 publication Critical patent/FR2389173B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Additionneur à sauvegarde des retenues pouvant exécuter des opérations d'addition, de décalage, de multiplication ou de division dans un système de traitement de données. Chaque position binaire de l'additionneur comprend une bascule déclenchée de somme 34 et une bascule déclenchée de retenue 36 qui fournissent les bits de pré-somme et de pré-retenue, chacune des bascules déclenchées comportant une bascule de mémoire de somme 26N ou de retenue 28N qui emmagasinent les valeurs de somme et de retenue respectivement pendant l'intervalle séparant les impulsions d'horloge. Cet additionneur est tel que chaque position binaire peut recevoir des bits d'entrée de somme et de retenue fournis par les bascules de la même position binaire ou d'une ou plusieurs autres positions binaires, selon l'opération arithmétique commandée par les signaux de commande
FR7809188A 1977-04-28 1978-03-23 Additionneur a sauvegarde des retenues Granted FR2389173A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/792,082 US4110832A (en) 1977-04-28 1977-04-28 Carry save adder

Publications (2)

Publication Number Publication Date
FR2389173A1 true FR2389173A1 (fr) 1978-11-24
FR2389173B1 FR2389173B1 (fr) 1981-08-14

Family

ID=25155736

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7809188A Granted FR2389173A1 (fr) 1977-04-28 1978-03-23 Additionneur a sauvegarde des retenues

Country Status (6)

Country Link
US (1) US4110832A (fr)
JP (1) JPS53135533A (fr)
DE (1) DE2814078A1 (fr)
FR (1) FR2389173A1 (fr)
GB (1) GB1549968A (fr)
IT (1) IT1108849B (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471454A (en) * 1981-10-27 1984-09-11 Ibm Corporation Fast, efficient, small adder
US4495593A (en) * 1982-07-01 1985-01-22 Hewlett-Packard Company Multiple bit encoding technique for combinational multipliers
US4550432A (en) * 1983-04-13 1985-10-29 At&T Bell Laboratories Image processor using a moment generator
US4700325A (en) * 1984-02-08 1987-10-13 Hewlett-Packard Company Binary tree calculations on monolithic integrated circuits
GB2161963B (en) * 1984-07-18 1988-02-03 Marconi Co Ltd Accumulator
US4623982A (en) 1985-06-10 1986-11-18 Hewlett-Packard Company Conditional carry techniques for digital processors
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
DE3787123D1 (de) * 1986-06-10 1993-09-30 Siemens Ag Anordnung zur bitparallelen Addition von Binärzahlen mit Carry-Save Überlaufkorrektur.
US5101370A (en) * 1990-07-26 1992-03-31 Unisys Corporation Programmable digital accumulate and scale circuit
JP2683488B2 (ja) * 1992-06-30 1997-11-26 インターナショナル・ビジネス・マシーンズ・コーポレイション ３−１論理演算装置
US5351207A (en) * 1992-08-31 1994-09-27 Intel Corporation Methods and apparatus for subtraction with 3:2 carry-save adders
US5619441A (en) * 1994-10-14 1997-04-08 International Business Machines Corporation High speed dynamic binary incrementer
JPH0962653A (ja) * 1995-08-29 1997-03-07 Mitsubishi Electric Corp 積和演算装置、積和演算器集積回路装置及び累積加算器
US6748410B1 (en) 1997-05-04 2004-06-08 M-Systems Flash Disk Pioneers, Ltd. Apparatus and method for modular multiplication and exponentiation based on montgomery multiplication
KR100684134B1 (ko) * 1997-05-04 2007-02-16 엠시스템스 리미티드 몽고메리 승산에 기초한 모듈의 승산 및 누승을 위한 개선된 장치와 방법
US6785703B2 (en) 2001-05-24 2004-08-31 International Business Machines Corporation Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology
US6591286B1 (en) 2002-01-18 2003-07-08 Neomagic Corp. Pipelined carry-lookahead generation for a fast incrementer
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US8214390B2 (en) * 2009-06-03 2012-07-03 Yahoo! Inc. Binary interest vector for better audience targeting
US11640397B2 (en) 2020-09-25 2023-05-02 Micron Technology, Inc. Acceleration of data queries in memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340388A (en) * 1965-07-12 1967-09-05 Ibm Latched carry save adder circuit for multipliers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3515344A (en) * 1966-08-31 1970-06-02 Ibm Apparatus for accumulating the sum of a plurality of operands
US3621218A (en) * 1967-09-29 1971-11-16 Hitachi Ltd High-speed divider utilizing carry save additions

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340388A (en) * 1965-07-12 1967-09-05 Ibm Latched carry save adder circuit for multipliers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/65 *
NO005026/70 *

Also Published As

Publication number Publication date
JPS5517425B2 (fr) 1980-05-12
FR2389173B1 (fr) 1981-08-14
IT7821398A0 (it) 1978-03-21
DE2814078A1 (de) 1978-11-09
JPS53135533A (en) 1978-11-27
US4110832A (en) 1978-08-29
IT1108849B (it) 1985-12-09
GB1549968A (en) 1979-08-08

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