FR2349883A1 - Systeme de traitement de donnees - Google Patents
Systeme de traitement de donneesInfo
- Publication number
- FR2349883A1 FR2349883A1 FR7707431A FR7707431A FR2349883A1 FR 2349883 A1 FR2349883 A1 FR 2349883A1 FR 7707431 A FR7707431 A FR 7707431A FR 7707431 A FR7707431 A FR 7707431A FR 2349883 A1 FR2349883 A1 FR 2349883A1
- Authority
- FR
- France
- Prior art keywords
- data
- command
- transfer
- simultaneous transfer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/682,228 US4053950A (en) | 1976-04-30 | 1976-04-30 | Residual status reporting during chained cycle steal input/output operations |
US05/682,229 US4038642A (en) | 1976-04-30 | 1976-04-30 | Input/output interface logic for concurrent operations |
US05/681,983 US4038641A (en) | 1976-04-30 | 1976-04-30 | Common polling logic for input/output interrupt or cycle steal data transfer requests |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2349883A1 true FR2349883A1 (fr) | 1977-11-25 |
FR2349883B1 FR2349883B1 (fr) | 1986-01-31 |
Family
ID=27418392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7707431A Expired FR2349883B1 (fr) | 1976-04-30 | 1977-03-04 | Systeme de traitement de donnees |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2349883B1 (fr) |
IT (1) | IT1115287B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2377064A1 (fr) * | 1977-01-06 | 1978-08-04 | Ibm | Circuit de raccordement d'interface d'entree/sortie |
-
1977
- 1977-03-04 FR FR7707431A patent/FR2349883B1/fr not_active Expired
- 1977-04-07 IT IT2219277A patent/IT1115287B/it active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2377064A1 (fr) * | 1977-01-06 | 1978-08-04 | Ibm | Circuit de raccordement d'interface d'entree/sortie |
Also Published As
Publication number | Publication date |
---|---|
IT1115287B (it) | 1986-02-03 |
FR2349883B1 (fr) | 1986-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |