FR2334204B1 - - Google Patents

Info

Publication number
FR2334204B1
FR2334204B1 FR7539998A FR7539998A FR2334204B1 FR 2334204 B1 FR2334204 B1 FR 2334204B1 FR 7539998 A FR7539998 A FR 7539998A FR 7539998 A FR7539998 A FR 7539998A FR 2334204 B1 FR2334204 B1 FR 2334204B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7539998A
Other languages
French (fr)
Other versions
FR2334204A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14879674A external-priority patent/JPS5426471B2/ja
Priority claimed from JP14879774A external-priority patent/JPS5415396B2/ja
Priority claimed from JP14879574A external-priority patent/JPS5513584B2/ja
Priority claimed from JP50001913A external-priority patent/JPS5182583A/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of FR2334204A1 publication Critical patent/FR2334204A1/fr
Application granted granted Critical
Publication of FR2334204B1 publication Critical patent/FR2334204B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65Integrated injection logic
    • H10P76/40
FR7539998A 1974-12-27 1975-12-29 Procede de fabrication d'un dispositif semi-conducteur en logique a injection integree Granted FR2334204A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP14879674A JPS5426471B2 (esLanguage) 1974-12-27 1974-12-27
JP14879774A JPS5415396B2 (esLanguage) 1974-12-27 1974-12-27
JP14879574A JPS5513584B2 (esLanguage) 1974-12-27 1974-12-27
JP50001913A JPS5182583A (en) 1974-12-27 1974-12-27 Handotaisochino seizohoho

Publications (2)

Publication Number Publication Date
FR2334204A1 FR2334204A1 (fr) 1977-07-01
FR2334204B1 true FR2334204B1 (esLanguage) 1978-05-26

Family

ID=27453504

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7539998A Granted FR2334204A1 (fr) 1974-12-27 1975-12-29 Procede de fabrication d'un dispositif semi-conducteur en logique a injection integree

Country Status (4)

Country Link
US (1) US4058419A (esLanguage)
DE (2) DE2558925C2 (esLanguage)
FR (1) FR2334204A1 (esLanguage)
GB (1) GB1528027A (esLanguage)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317081A (en) * 1976-07-30 1978-02-16 Sharp Corp Production of i2l device
DE2652103C2 (de) * 1976-11-16 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Integrierte Halbleiteranordnung für ein logisches Schaltungskonzept und Verfahren zu ihrer Herstellung
US4180827A (en) * 1977-08-31 1979-12-25 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
CA1116309A (en) * 1977-11-30 1982-01-12 David L. Bergeron Structure and process for optimizing the characteristics of i.sup.2l devices
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques
US4317690A (en) * 1980-06-18 1982-03-02 Signetics Corporation Self-aligned double polysilicon MOS fabrication
US4446611A (en) * 1980-06-26 1984-05-08 International Business Machines Corporation Method of making a saturation-limited bipolar transistor device
DE3136731A1 (de) * 1981-09-16 1983-03-31 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
US5759902A (en) * 1986-09-26 1998-06-02 Analog Devices, Incorporated Method of making an integrated circuit with complementary junction-isolated bipolar transistors
CN102299070A (zh) * 2010-06-22 2011-12-28 无锡华润上华半导体有限公司 横向pnp晶体管的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328214A (en) * 1963-04-22 1967-06-27 Siliconix Inc Process for manufacturing horizontal transistor structure
US3472710A (en) * 1967-04-20 1969-10-14 Teledyne Inc Method of forming a field effect transistor
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices
DE2034371A1 (de) * 1969-07-12 1971-01-28 Tokyo Shibaura Electric Co Ltd , Kawasaki (Japan) Verfahren zur Herstellung von Halb leitervornchtungen
DE2262297C2 (de) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau
US3919005A (en) * 1973-05-07 1975-11-11 Fairchild Camera Instr Co Method for fabricating double-diffused, lateral transistor
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
GB1507061A (en) * 1974-03-26 1978-04-12 Signetics Corp Semiconductors
US3982266A (en) * 1974-12-09 1976-09-21 Texas Instruments Incorporated Integrated injection logic having high inverse current gain

Also Published As

Publication number Publication date
GB1528027A (en) 1978-10-11
US4058419A (en) 1977-11-15
DE2558925C2 (de) 1985-10-31
DE2558925A1 (de) 1976-07-08
FR2334204A1 (fr) 1977-07-01
DE2560576C2 (de) 1985-10-31

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