FR2330245A1 - PROCESS FOR DEPOSITING CONDUCTIVE LAYERS ON SUBSTRATES AND PRODUCTS OBTAINED BY THE PROCESS - Google Patents

PROCESS FOR DEPOSITING CONDUCTIVE LAYERS ON SUBSTRATES AND PRODUCTS OBTAINED BY THE PROCESS

Info

Publication number
FR2330245A1
FR2330245A1 FR7632825A FR7632825A FR2330245A1 FR 2330245 A1 FR2330245 A1 FR 2330245A1 FR 7632825 A FR7632825 A FR 7632825A FR 7632825 A FR7632825 A FR 7632825A FR 2330245 A1 FR2330245 A1 FR 2330245A1
Authority
FR
France
Prior art keywords
substrates
conductive layers
products obtained
depositing conductive
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7632825A
Other languages
French (fr)
Other versions
FR2330245B3 (en
Inventor
Paul Howard Holloway
Donald Moss Mattox
Gerald Clifford Nelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Department of Energy
Energy Research and Development Administration ERDA
Original Assignee
US Department of Energy
Energy Research and Development Administration ERDA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Department of Energy, Energy Research and Development Administration ERDA filed Critical US Department of Energy
Publication of FR2330245A1 publication Critical patent/FR2330245A1/en
Application granted granted Critical
Publication of FR2330245B3 publication Critical patent/FR2330245B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
FR7632825A 1975-10-30 1976-10-29 PROCESS FOR DEPOSITING CONDUCTIVE LAYERS ON SUBSTRATES AND PRODUCTS OBTAINED BY THE PROCESS Granted FR2330245A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62742075A 1975-10-30 1975-10-30

Publications (2)

Publication Number Publication Date
FR2330245A1 true FR2330245A1 (en) 1977-05-27
FR2330245B3 FR2330245B3 (en) 1979-07-13

Family

ID=24514575

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7632825A Granted FR2330245A1 (en) 1975-10-30 1976-10-29 PROCESS FOR DEPOSITING CONDUCTIVE LAYERS ON SUBSTRATES AND PRODUCTS OBTAINED BY THE PROCESS

Country Status (5)

Country Link
JP (1) JPS5257972A (en)
CA (1) CA1058330A (en)
DE (1) DE2649091A1 (en)
FR (1) FR2330245A1 (en)
GB (1) GB1539272A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074605A2 (en) * 1981-09-11 1983-03-23 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
FR2542502A1 (en) * 1983-03-11 1984-09-14 Nec Corp SUBSTRATE HAVING AT LEAST ONE FINE CONDUCTIVE LAYER
EP0336869A2 (en) * 1988-04-08 1989-10-11 International Business Machines Corporation A multilayered metallurgical structure for an electronic component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074605A2 (en) * 1981-09-11 1983-03-23 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
EP0074605A3 (en) * 1981-09-11 1985-03-20 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
FR2542502A1 (en) * 1983-03-11 1984-09-14 Nec Corp SUBSTRATE HAVING AT LEAST ONE FINE CONDUCTIVE LAYER
EP0336869A2 (en) * 1988-04-08 1989-10-11 International Business Machines Corporation A multilayered metallurgical structure for an electronic component
EP0336869A3 (en) * 1988-04-08 1991-05-02 International Business Machines Corporation A multilayered metallurgical structure for an electronic component

Also Published As

Publication number Publication date
GB1539272A (en) 1979-01-31
FR2330245B3 (en) 1979-07-13
JPS5257972A (en) 1977-05-12
CA1058330A (en) 1979-07-10
DE2649091A1 (en) 1977-05-12

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Legal Events

Date Code Title Description
ST Notification of lapse