FR2311385A1 - Memoire a decalage - Google Patents

Memoire a decalage

Info

Publication number
FR2311385A1
FR2311385A1 FR7515116A FR7515116A FR2311385A1 FR 2311385 A1 FR2311385 A1 FR 2311385A1 FR 7515116 A FR7515116 A FR 7515116A FR 7515116 A FR7515116 A FR 7515116A FR 2311385 A1 FR2311385 A1 FR 2311385A1
Authority
FR
France
Prior art keywords
memory
telecommunications system
closed chain
memory modules
bus line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7515116A
Other languages
English (en)
Inventor
Patrice Bernard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TECSI RESEAUX
Original Assignee
TECSI RESEAUX
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TECSI RESEAUX filed Critical TECSI RESEAUX
Priority to FR7515116A priority Critical patent/FR2311385A1/fr
Publication of FR2311385A1 publication Critical patent/FR2311385A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Exchange Systems With Centralized Control (AREA)
FR7515116A 1975-05-15 1975-05-15 Memoire a decalage Withdrawn FR2311385A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7515116A FR2311385A1 (fr) 1975-05-15 1975-05-15 Memoire a decalage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7515116A FR2311385A1 (fr) 1975-05-15 1975-05-15 Memoire a decalage

Publications (1)

Publication Number Publication Date
FR2311385A1 true FR2311385A1 (fr) 1976-12-10

Family

ID=9155264

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7515116A Withdrawn FR2311385A1 (fr) 1975-05-15 1975-05-15 Memoire a decalage

Country Status (1)

Country Link
FR (1) FR2311385A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982002451A1 (fr) * 1981-01-07 1982-07-22 Corp Burroughs Ameliorations aux memoires a circuits integres a echelle de tranche
US4471483A (en) * 1980-08-21 1984-09-11 Burroughs Corporation Branched labyrinth wafer-scale integrated circuit
US4489397A (en) * 1980-08-21 1984-12-18 Burroughs Corporation Chain configurable polycellular wafer scale integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471483A (en) * 1980-08-21 1984-09-11 Burroughs Corporation Branched labyrinth wafer-scale integrated circuit
US4489397A (en) * 1980-08-21 1984-12-18 Burroughs Corporation Chain configurable polycellular wafer scale integrated circuit
WO1982002451A1 (fr) * 1981-01-07 1982-07-22 Corp Burroughs Ameliorations aux memoires a circuits integres a echelle de tranche
US4528647A (en) * 1981-01-07 1985-07-09 Burroughs Corp. Wafer scale integrated circuit memories

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Legal Events

Date Code Title Description
ST Notification of lapse