FR2309078A1 - Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock - Google Patents

Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock

Info

Publication number
FR2309078A1
FR2309078A1 FR7513085A FR7513085A FR2309078A1 FR 2309078 A1 FR2309078 A1 FR 2309078A1 FR 7513085 A FR7513085 A FR 7513085A FR 7513085 A FR7513085 A FR 7513085A FR 2309078 A1 FR2309078 A1 FR 2309078A1
Authority
FR
France
Prior art keywords
clock
local clock
binary coded
phase control
fitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7513085A
Other languages
French (fr)
Other versions
FR2309078B1 (en
Inventor
Michel Abraham
Claude Pivon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7513085A priority Critical patent/FR2309078A1/en
Priority to BE1007315A priority patent/BE840440A/en
Priority to DE19762617222 priority patent/DE2617222A1/en
Publication of FR2309078A1 publication Critical patent/FR2309078A1/en
Application granted granted Critical
Publication of FR2309078B1 publication Critical patent/FR2309078B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/16—Digital recording or reproducing using non self-clocking codes, i.e. the clock signals are either recorded in a separate clocking track or in a combination of several information tracks

Abstract

The circuit for reconstituting the clock signal for a binary coded transmission having a given clock frequency uses a transition detector, providing a pulse in response to each signal transition. A slave loop controls the phase of a local clock having the same frequency as the block frequency of the transmission, the loop including a comparator for comparing the phase of the transition pulses with the phase of the local clock, to provide two sets of advance and delay pulses respectively. The pulses from the comparator are supplied to phase control means for the local clock, using two stochastic filters.
FR7513085A 1975-04-25 1975-04-25 Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock Granted FR2309078A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR7513085A FR2309078A1 (en) 1975-04-25 1975-04-25 Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock
BE1007315A BE840440A (en) 1975-04-25 1976-04-07 DEVICE FOR RECONSTRUCTING THE RATE CLOCK OF AN NRZ MESSAGE
DE19762617222 DE2617222A1 (en) 1975-04-25 1976-04-20 DEVICE FOR RECOVERING THE CYCLE SPEED OF AN NRZ ENCRYPTED MESSAGE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7513085A FR2309078A1 (en) 1975-04-25 1975-04-25 Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock

Publications (2)

Publication Number Publication Date
FR2309078A1 true FR2309078A1 (en) 1976-11-19
FR2309078B1 FR2309078B1 (en) 1977-11-10

Family

ID=9154517

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7513085A Granted FR2309078A1 (en) 1975-04-25 1975-04-25 Clock signal reconstituting circuit - for binary coded transmission is fitted with transition detector and phase control loop for local clock

Country Status (3)

Country Link
BE (1) BE840440A (en)
DE (1) DE2617222A1 (en)
FR (1) FR2309078A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985002041A1 (en) * 1983-11-04 1985-05-09 Inmos Limited Communication interface

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3537477A1 (en) * 1985-10-22 1987-04-23 Porsche Ag ARRANGEMENT FOR INDIVIDUALLY ADAPTING A SERIAL INTERFACE OF A DATA PROCESSING SYSTEM TO A DATA TRANSMISSION SPEED OF A COMMUNICATION PARTNER

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1146911B (en) * 1962-08-07 1963-04-11 Siemens Ag Procedure for a recipient for synchronously transmitted telegraphic characters
US3290611A (en) * 1965-09-14 1966-12-06 Bell Telephone Labor Inc Digital frequency control circuit
GB1212213A (en) * 1967-11-21 1970-11-11 Int Computers Ltd Improvements in or relating to clock synchronising circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1146911B (en) * 1962-08-07 1963-04-11 Siemens Ag Procedure for a recipient for synchronously transmitted telegraphic characters
US3290611A (en) * 1965-09-14 1966-12-06 Bell Telephone Labor Inc Digital frequency control circuit
GB1212213A (en) * 1967-11-21 1970-11-11 Int Computers Ltd Improvements in or relating to clock synchronising circuits

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS, 9 JANVIER 1975, VOL. 48, NO. 1. ARTICLE DE ANDERSON "DUAL BANDWIDTH LOOP SPEEDS PHASE LOCK", PAGES 116 A 117 *
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-20, NO. 2, AVRIL 1972 ARTICLE DE CESSNA: "PHASE NOISE AND TRANSIENT TIMES FOR A BINARY QUANTIZED DIGITAL PHASE-LOCKED LOOP IN WHITE GAUSSIAN NOISE", PAGES 94-104) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985002041A1 (en) * 1983-11-04 1985-05-09 Inmos Limited Communication interface

Also Published As

Publication number Publication date
BE840440A (en) 1976-10-07
DE2617222A1 (en) 1976-11-11
FR2309078B1 (en) 1977-11-10

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Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse