GB1292340A - Method of and circuitry for the generation of the timing signal of a pulse sequence and the regeneration of the pulse sequence - Google Patents

Method of and circuitry for the generation of the timing signal of a pulse sequence and the regeneration of the pulse sequence

Info

Publication number
GB1292340A
GB1292340A GB5159769A GB5159769A GB1292340A GB 1292340 A GB1292340 A GB 1292340A GB 5159769 A GB5159769 A GB 5159769A GB 5159769 A GB5159769 A GB 5159769A GB 1292340 A GB1292340 A GB 1292340A
Authority
GB
United Kingdom
Prior art keywords
stage
period
divide
pulse sequence
discrimination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5159769A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ORION RADIO
Original Assignee
ORION RADIO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ORION RADIO filed Critical ORION RADIO
Publication of GB1292340A publication Critical patent/GB1292340A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Abstract

1292340 Automatic phase control ORION RADIO ES VILLAMOSSAGI VALLALAT 21 Oct 1969 [21 Oct 1968] 51597/69 Heading H3A A system for synchronizing a local clock signal with a received data signal of the type in which the synchronization is effected by controlling a divider which produces the local clock is characterized in that the output signal from the final stage of the divider is divided into a " discrimination" period and a variable length "intervention" period, the length of the latter being adjusted whenever the phase error detected during the discrimination period exceeds a predetermined value and the sense of the adjustment depending on the sign of the phase error. As described with reference to Fig. 2, pulses from oscillator 1 are fed through divide-by-two stage 2, divide-by-five stage 3, and final divide-by-two stage 4 to produce pulses at the required clock rate, and the output from the stage 4 is divided into the. two required periods by gating it with the output from stage 3 in comparator 5. If the phase difference between the input signal 9 and that from the stage 4 is such that a transition of the input signal occurs during the discrimination period, bi-stable 35 is set, thus enabling the logic circuit 31 . . . 34 to produce appropriate signals on lines 19, 20 to change the division factor of stage 2 so that the chain divides by 19 or 21 as required instead of 20.
GB5159769A 1968-10-21 1969-10-21 Method of and circuitry for the generation of the timing signal of a pulse sequence and the regeneration of the pulse sequence Expired GB1292340A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
HUOR001113 1968-10-21

Publications (1)

Publication Number Publication Date
GB1292340A true GB1292340A (en) 1972-10-11

Family

ID=11000334

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5159769A Expired GB1292340A (en) 1968-10-21 1969-10-21 Method of and circuitry for the generation of the timing signal of a pulse sequence and the regeneration of the pulse sequence

Country Status (4)

Country Link
DE (1) DE1951579A1 (en)
FR (1) FR2021153A1 (en)
GB (1) GB1292340A (en)
NL (1) NL6915836A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3694752A (en) * 1971-03-18 1972-09-26 North American Rockwell High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
FR2221861A1 (en) * 1972-12-29 1974-10-11 Teletransmissions Cie Eu Detection of frequency, phase and amplitude modulated signals - uses an analog-digital converter and binary memory

Also Published As

Publication number Publication date
DE1951579A1 (en) 1970-04-23
NL6915836A (en) 1970-04-23
FR2021153A1 (en) 1970-07-17

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee