FR2292333A1 - Transistors and integrated circuits prodn. - by masking and etching process giving accurately placed (sub)micron alloyed zones - Google Patents

Transistors and integrated circuits prodn. - by masking and etching process giving accurately placed (sub)micron alloyed zones

Info

Publication number
FR2292333A1
FR2292333A1 FR7535846A FR7535846A FR2292333A1 FR 2292333 A1 FR2292333 A1 FR 2292333A1 FR 7535846 A FR7535846 A FR 7535846A FR 7535846 A FR7535846 A FR 7535846A FR 2292333 A1 FR2292333 A1 FR 2292333A1
Authority
FR
France
Prior art keywords
prodn
micron
sub
integrated circuits
masking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7535846A
Other languages
French (fr)
Other versions
FR2292333B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STYAPAS STYAPONO
Original Assignee
STYAPAS STYAPONO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SU742076968A external-priority patent/SU653647A1/en
Priority claimed from SU7402076899A external-priority patent/SU521802A1/en
Application filed by STYAPAS STYAPONO filed Critical STYAPAS STYAPONO
Publication of FR2292333A1 publication Critical patent/FR2292333A1/en
Application granted granted Critical
Publication of FR2292333B1 publication Critical patent/FR2292333B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

In the prodn. of semiconductor elements by applying at least 2 layers to a substrate of the first conductivity type, one layer acting as alloying layer and the other as masking layer, on which a photoresist pattern is produced, forming a technological structure by removing part of the layers down to the substrate, to give an insulating layer around this, forming a zone of the second conductivity type by diffusion of a dopant from the alloying layer, by opening windows in the technological structure, diffusing the dopant at least through one window and producing a metallised pattern on it, the windows are formed by removing at least 2 areas at the periphery of the technological structure down to the substrate. Used for the prodn. of transistor structures and integrated circuits with accurate mutual arrangement of the alloyed zones with micron and sub-micron dimensions.
FR7535846A 1974-11-25 1975-11-24 Transistors and integrated circuits prodn. - by masking and etching process giving accurately placed (sub)micron alloyed zones Granted FR2292333A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SU742076968A SU653647A1 (en) 1974-11-25 1974-11-25 Method of forming base source at manufacturing transistor structures
SU7402076899A SU521802A1 (en) 1974-11-25 1974-11-25 Method of selective forming of base source at making transistor structures

Publications (2)

Publication Number Publication Date
FR2292333A1 true FR2292333A1 (en) 1976-06-18
FR2292333B1 FR2292333B1 (en) 1979-02-02

Family

ID=26665540

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7535846A Granted FR2292333A1 (en) 1974-11-25 1975-11-24 Transistors and integrated circuits prodn. - by masking and etching process giving accurately placed (sub)micron alloyed zones

Country Status (5)

Country Link
CS (1) CS180949B1 (en)
DD (1) DD121429A5 (en)
DE (1) DE2552641B2 (en)
FR (1) FR2292333A1 (en)
HU (1) HU172486B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2454698A1 (en) * 1979-04-20 1980-11-14 Radiotechnique Compelec METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEANT *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2454698A1 (en) * 1979-04-20 1980-11-14 Radiotechnique Compelec METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD

Also Published As

Publication number Publication date
FR2292333B1 (en) 1979-02-02
DE2552641B2 (en) 1979-03-29
CS180949B1 (en) 1978-02-28
DE2552641A1 (en) 1976-06-10
DD121429A5 (en) 1976-07-20
HU172486B (en) 1978-09-28

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Legal Events

Date Code Title Description
ST Notification of lapse