FR2277411A1 - Circuits de prepositionnement pour circuits integres en technologie mos - Google Patents

Circuits de prepositionnement pour circuits integres en technologie mos

Info

Publication number
FR2277411A1
FR2277411A1 FR7520520A FR7520520A FR2277411A1 FR 2277411 A1 FR2277411 A1 FR 2277411A1 FR 7520520 A FR7520520 A FR 7520520A FR 7520520 A FR7520520 A FR 7520520A FR 2277411 A1 FR2277411 A1 FR 2277411A1
Authority
FR
France
Prior art keywords
circuits
prepositioning
mos technology
technology integrated
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7520520A
Other languages
English (en)
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2277411A1 publication Critical patent/FR2277411A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Logic Circuits (AREA)
FR7520520A 1974-07-01 1975-06-30 Circuits de prepositionnement pour circuits integres en technologie mos Withdrawn FR2277411A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/485,191 US3942162A (en) 1974-07-01 1974-07-01 Pre-conditioning circuits for MOS integrated circuits

Publications (1)

Publication Number Publication Date
FR2277411A1 true FR2277411A1 (fr) 1976-01-30

Family

ID=23927249

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7520520A Withdrawn FR2277411A1 (fr) 1974-07-01 1975-06-30 Circuits de prepositionnement pour circuits integres en technologie mos

Country Status (4)

Country Link
US (1) US3942162A (cg-RX-API-DMAC7.html)
JP (1) JPS5824879B2 (cg-RX-API-DMAC7.html)
DE (1) DE2528066A1 (cg-RX-API-DMAC7.html)
FR (1) FR2277411A1 (cg-RX-API-DMAC7.html)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4006457A (en) * 1975-02-18 1977-02-01 Motorola, Inc. Logic circuitry for selection of dedicated registers
JPS52146274A (en) * 1976-05-31 1977-12-05 Toshiba Corp Output circuit
US4100430A (en) * 1977-03-07 1978-07-11 Rockwell International Corporation Multi-phase and gate
US4291393A (en) * 1980-02-11 1981-09-22 Mostek Corporation Active refresh circuit for dynamic MOS circuits
JPS5837636B2 (ja) * 1980-07-31 1983-08-17 富士通株式会社 半導体記憶装置
US4330722A (en) * 1980-08-18 1982-05-18 Bell Telephone Laboratories, Incorporated Clocked IGFET logic circuit
US4405996A (en) * 1981-02-06 1983-09-20 Rca Corporation Precharge with power conservation
JPS5968889A (ja) * 1982-10-08 1984-04-18 Toshiba Corp 半導体記憶装置
JPS59221891A (ja) * 1983-05-31 1984-12-13 Toshiba Corp スタテイツク型半導体記憶装置
DE3328387A1 (de) * 1983-08-05 1985-02-14 Siemens AG, 1000 Berlin und 8000 München Schaltverfahren fuer fernmeldevermittlungsanlagen, insbesondere fernsprechvermittlungsanlagen, mit informationsverarbeitenden schalteinrichtungen und mit ihnen zusammenarbeitenden arbeitsspeichern
US4712194A (en) * 1984-06-08 1987-12-08 Matsushita Electric Industrial Co., Ltd. Static random access memory
JPS6124091A (ja) * 1984-07-12 1986-02-01 Nec Corp メモリ回路
US4638462A (en) * 1985-01-31 1987-01-20 International Business Machines Corporation Self-timed precharge circuit
JPS63263689A (ja) * 1987-04-20 1988-10-31 Mitsubishi Electric Corp 半導体記憶装置
EP0426597B1 (en) * 1989-10-30 1995-11-08 International Business Machines Corporation Bit decode scheme for memory arrays
US5022010A (en) * 1989-10-30 1991-06-04 International Business Machines Corporation Word decoder for a memory array
KR101033490B1 (ko) * 2009-11-30 2011-05-09 주식회사 하이닉스반도체 패드를 선택적으로 이용하는 반도체 메모리 장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786437A (en) * 1972-01-03 1974-01-15 Honeywell Inf Systems Random access memory system utilizing an inverting cell concept
US3801964A (en) * 1972-02-24 1974-04-02 Advanced Memory Sys Inc Semiconductor memory with address decoding
US3771147A (en) * 1972-12-04 1973-11-06 Bell Telephone Labor Inc Igfet memory system

Also Published As

Publication number Publication date
US3942162A (en) 1976-03-02
DE2528066A1 (de) 1976-01-22
JPS5824879B2 (ja) 1983-05-24
JPS5125940A (cg-RX-API-DMAC7.html) 1976-03-03

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Legal Events

Date Code Title Description
ST Notification of lapse