FR2277376A1 - Dispositif de calcul binaire parallele effectuant des operations d'addition et de soustraction - Google Patents

Dispositif de calcul binaire parallele effectuant des operations d'addition et de soustraction

Info

Publication number
FR2277376A1
FR2277376A1 FR7517190A FR7517190A FR2277376A1 FR 2277376 A1 FR2277376 A1 FR 2277376A1 FR 7517190 A FR7517190 A FR 7517190A FR 7517190 A FR7517190 A FR 7517190A FR 2277376 A1 FR2277376 A1 FR 2277376A1
Authority
FR
France
Prior art keywords
calculation device
device performing
performing addition
subtraction operations
parallel binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7517190A
Other languages
English (en)
Other versions
FR2277376B1 (fr
Inventor
Hellmuth R Geng
Johann Hajdu
Guenter Knauft
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19742432450 external-priority patent/DE2432450C2/de
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2277376A1 publication Critical patent/FR2277376A1/fr
Application granted granted Critical
Publication of FR2277376B1 publication Critical patent/FR2277376B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7517190A 1974-07-06 1975-05-27 Dispositif de calcul binaire parallele effectuant des operations d'addition et de soustraction Granted FR2277376A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742432450 DE2432450C2 (de) 1974-07-06 Binäres Parallelrechenwerk für Additionen oder Subtraktionen

Publications (2)

Publication Number Publication Date
FR2277376A1 true FR2277376A1 (fr) 1976-01-30
FR2277376B1 FR2277376B1 (fr) 1977-07-08

Family

ID=5919845

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7517190A Granted FR2277376A1 (fr) 1974-07-06 1975-05-27 Dispositif de calcul binaire parallele effectuant des operations d'addition et de soustraction

Country Status (4)

Country Link
US (1) US3947671A (fr)
JP (1) JPS5115344A (fr)
FR (1) FR2277376A1 (fr)
IT (1) IT1038941B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319335A (en) * 1979-10-16 1982-03-09 Burroughs Corporation Arithmetic logic unit controller
US4338676A (en) * 1980-07-14 1982-07-06 Bell Telephone Laboratories, Incorporated Asynchronous adder circuit
US4623981A (en) * 1983-09-20 1986-11-18 Digital Equipment Corporation ALU with carry length detection
US4707783A (en) * 1984-10-19 1987-11-17 Amdahl Corporation Ancillary execution unit for a pipelined data processing system
US4885716A (en) * 1988-08-15 1989-12-05 Dallas Semiconductor Corporation High speed carry chain
JPH02259926A (ja) * 1989-03-31 1990-10-22 Hitachi Ltd 加算制御方式
US5327368A (en) * 1989-06-23 1994-07-05 Digital Equipment Corporation Chunky binary multiplier and method of operation
DE19639935C1 (de) * 1996-09-27 1998-04-23 Siemens Ag Schaltungsanordnung mit zwischen Registern angeordneten kombinatorischen Blöcken
AU2002317928A1 (en) * 2001-06-13 2003-05-19 Zencod S.A. Cryptographic processing accelerator board
RU2628180C1 (ru) * 2016-10-03 2017-08-15 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Арифметико-логическое устройство для сложения чисел по модулю
RU2628175C1 (ru) * 2016-10-12 2017-08-15 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Арифметико-логическое устройство для вычитания чисел по модулю

Also Published As

Publication number Publication date
JPS5115344A (en) 1976-02-06
JPS5426462B2 (fr) 1979-09-04
DE2432450A1 (fr) 1975-12-04
IT1038941B (it) 1979-11-30
FR2277376B1 (fr) 1977-07-08
US3947671A (en) 1976-03-30
DE2432450B1 (de) 1975-12-04

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Legal Events

Date Code Title Description
ST Notification of lapse