FR2236229A1 - - Google Patents

Info

Publication number
FR2236229A1
FR2236229A1 FR7418500A FR7418500A FR2236229A1 FR 2236229 A1 FR2236229 A1 FR 2236229A1 FR 7418500 A FR7418500 A FR 7418500A FR 7418500 A FR7418500 A FR 7418500A FR 2236229 A1 FR2236229 A1 FR 2236229A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7418500A
Other versions
FR2236229B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2236229A1 publication Critical patent/FR2236229A1/fr
Application granted granted Critical
Publication of FR2236229B1 publication Critical patent/FR2236229B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
FR7418500A 1973-07-02 1974-05-21 Expired FR2236229B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00376078A US3839706A (en) 1973-07-02 1973-07-02 Input/output channel relocation storage protect mechanism

Publications (2)

Publication Number Publication Date
FR2236229A1 true FR2236229A1 (fr) 1975-01-31
FR2236229B1 FR2236229B1 (fr) 1976-12-24

Family

ID=23483624

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7418500A Expired FR2236229B1 (fr) 1973-07-02 1974-05-21

Country Status (5)

Country Link
US (1) US3839706A (fr)
JP (1) JPS553739B2 (fr)
DE (1) DE2431520A1 (fr)
FR (1) FR2236229B1 (fr)
GB (1) GB1453348A (fr)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433822B2 (fr) * 1974-02-22 1979-10-23
US4300192A (en) * 1974-04-18 1981-11-10 Honeywell Information Systems Inc. Method and means for storing and accessing information in a shared access multiprogrammed data processing system
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
JPS5615066B2 (fr) * 1974-06-13 1981-04-08
US4017839A (en) * 1975-06-30 1977-04-12 Honeywell Information Systems, Inc. Input/output multiplexer security system
JPS52130532A (en) * 1976-04-27 1977-11-01 Fujitsu Ltd Address conversion system
US4053948A (en) * 1976-06-21 1977-10-11 Ibm Corporation Look aside array invalidation mechanism
JPS533024A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533027A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533025A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533026A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533028A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
US4093986A (en) * 1976-12-27 1978-06-06 International Business Machines Corporation Address translation with storage protection
JPS5384525A (en) * 1976-12-29 1978-07-26 Fujitsu Ltd Dynamic address convertor
US4091445A (en) * 1977-01-18 1978-05-23 Honeywell Information Systems Inc. Program switching monitor
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
JPS5474632A (en) * 1977-11-28 1979-06-14 Nec Corp Data processor
US4241401A (en) * 1977-12-19 1980-12-23 Sperry Corporation Virtual address translator utilizing interrupt level code
FR2430041A1 (fr) * 1978-06-28 1980-01-25 Fujitsu Ltd Dispositif de traduction dynamique d'adresse
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
US4228504A (en) * 1978-10-23 1980-10-14 International Business Machines Corporation Virtual addressing for I/O adapters
US4231088A (en) * 1978-10-23 1980-10-28 International Business Machines Corporation Allocating and resolving next virtual pages for input/output
CA1123964A (fr) * 1978-10-26 1982-05-18 Anthony J. Capozzi Hierarchie integree de stockage a niveaux multiples pour systeme de traitement de donnees
JPS5640938A (en) * 1979-09-12 1981-04-17 Nec Corp Input/output control unit
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
US4507781A (en) * 1980-03-14 1985-03-26 Ibm Corporation Time domain multiple access broadcasting, multipoint, and conferencing communication apparatus and method
US4468729A (en) * 1981-06-29 1984-08-28 Sperry Corporation Automatic memory module address assignment system for available memory modules
US4439830A (en) * 1981-11-09 1984-03-27 Control Data Corporation Computer system key and lock protection mechanism
JPS5924485A (ja) * 1982-07-30 1984-02-08 Toshiba Corp 入出力ペ−ジング機構
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
JPH0821009B2 (ja) * 1986-09-22 1996-03-04 日本電気株式会社 チャネル制御装置のイニシャライズ方法及びそのイニシャライズのためのシステム
DE3781406T2 (de) * 1987-06-09 1993-04-01 Ibm Steuerungsschema fuer segmentierte puffer, gegruendet auf gemeinsam genutzter referenzzaehlung.
FR2630838A2 (fr) * 1987-07-15 1989-11-03 Centre Nat Rech Scient Unite de gestion d'acces en memoire, a identifiants logiques invariants, notamment pour la gestion de bases de donnees, et procede de gestion d'acces correspondant
US5278963A (en) * 1991-06-21 1994-01-11 International Business Machines Corporation Pretranslation of virtual addresses prior to page crossing
US5461721A (en) * 1993-04-14 1995-10-24 International Business Machines Corporation System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs)
CA2137488C (fr) * 1994-02-18 1998-09-29 Richard I. Baum Methode et dispositif pour executer des traitements paralleles dans les systemes de traitement de donnees courants
JPH0997214A (ja) * 1995-09-29 1997-04-08 Internatl Business Mach Corp <Ibm> 補助プロセッサのためのアドレス変換を含む情報処理システム
US6249867B1 (en) * 1998-07-31 2001-06-19 Lucent Technologies Inc. Method for transferring sensitive information using initially unsecured communication
US6553477B1 (en) * 2000-11-06 2003-04-22 Fujitsu Limited Microprocessor and address translation method for microprocessor
DE102004022264A1 (de) * 2004-05-06 2005-12-01 Witty-Chemie Gmbh & Co. Kg Aktivkohlezusammensetzung und deren Verwendung zur Aufbereitung von Schwimmbadwasser
US9164923B2 (en) * 2011-07-01 2015-10-20 Intel Corporation Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2145982A5 (fr) * 1971-07-13 1973-02-23 Ibm

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573736A (en) * 1968-01-15 1971-04-06 Ibm Interruption and interlock arrangement
DE2064383C3 (de) * 1970-01-12 1981-02-26 Fujitsu Ltd., Kawasaki, Kanagawa (Japan) Datenverarbeitungsanlage mit mehreren zentralen Verarbeitungseinrichtungen
US3675209A (en) * 1970-02-06 1972-07-04 Burroughs Corp Autonomous multiple-path input/output control system
US3704453A (en) * 1971-02-23 1972-11-28 Ibm Catenated files
US3725864A (en) * 1971-03-03 1973-04-03 Ibm Input/output control

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2145982A5 (fr) * 1971-07-13 1973-02-23 Ibm

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
(UE US: "IBM TECHNICAL DISCLOSURE BULLETIN", VOLUME 14, NO.1, JUIN 1971, PAGES 214 A 216, ARTICLE: "SYSTEM RELOCATION METHOD" JAMES ET AUTRES ) *
OUTPUT SUBSYSTEM CHANNEL TRANSLATION BUFFERING" LARSON *
UE US: "COMMUNICATION OF THE ACM", VOLUME 13, NO.12, DECEMBRE 1970, PAGES 727 A 733, ARTICLE "PROCESS MANAGEMENT AND RESSOURCE SHARING IN THE MULTIACCESS SYSTEM ESOPE" BETOURNE ETAUTRES ) *
UE US: "IBM TECHNICAL DISCLOSURE BULLETIN", VOLUME 15, NO.5, OCTOBRE 1972, PAGES 1458 A 1460A, ARTICLE: "INPUT *

Also Published As

Publication number Publication date
DE2431520A1 (de) 1975-01-30
US3839706A (en) 1974-10-01
JPS553739B2 (fr) 1980-01-26
FR2236229B1 (fr) 1976-12-24
GB1453348A (en) 1976-10-20
JPS5069941A (fr) 1975-06-11

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Legal Events

Date Code Title Description
ST Notification of lapse