FR2210799A1 - - Google Patents

Info

Publication number
FR2210799A1
FR2210799A1 FR7344135A FR7344135A FR2210799A1 FR 2210799 A1 FR2210799 A1 FR 2210799A1 FR 7344135 A FR7344135 A FR 7344135A FR 7344135 A FR7344135 A FR 7344135A FR 2210799 A1 FR2210799 A1 FR 2210799A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7344135A
Other versions
FR2210799B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2210799A1 publication Critical patent/FR2210799A1/fr
Application granted granted Critical
Publication of FR2210799B1 publication Critical patent/FR2210799B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
FR7344135A 1972-12-13 1973-12-11 Expired FR2210799B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12543272A JPS5710516B2 (fr) 1972-12-13 1972-12-13

Publications (2)

Publication Number Publication Date
FR2210799A1 true FR2210799A1 (fr) 1974-07-12
FR2210799B1 FR2210799B1 (fr) 1977-08-12

Family

ID=14909934

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7344135A Expired FR2210799B1 (fr) 1972-12-13 1973-12-11

Country Status (4)

Country Link
US (1) US3893086A (fr)
JP (1) JPS5710516B2 (fr)
FR (1) FR2210799B1 (fr)
GB (1) GB1452306A (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2442132C3 (de) * 1974-09-03 1981-11-05 Siemens AG, 1000 Berlin und 8000 München Dynamisches Schieberegister und Verfahren zu seinem Betrieb
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
JPS6012718B2 (ja) * 1980-03-28 1985-04-03 富士通株式会社 半導体ダイナミックメモリ
US4419592A (en) * 1980-07-21 1983-12-06 International Business Machines Corporation Bidirection data switch sequencing circuit
JPS57164331A (en) * 1981-04-02 1982-10-08 Nec Corp Buffer controller
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
US4679213A (en) * 1985-01-08 1987-07-07 Sutherland Ivan E Asynchronous queue system
US4907187A (en) * 1985-05-17 1990-03-06 Sanyo Electric Co., Ltd. Processing system using cascaded latches in a transmission path for both feedback and forward transfer of data
UA111169C2 (uk) 2013-03-15 2016-04-11 Анатолій Анатолійович Новіков Спосіб роботи np-процесора

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3166715A (en) * 1962-09-06 1965-01-19 Sperry Rand Corp Asynchronous self controlled shift register

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1933907A1 (de) * 1969-07-03 1971-03-11 Siemens Ag Pufferspeicher
US3736570A (en) * 1971-11-04 1973-05-29 Zenith Radio Corp Multiple state memory circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3166715A (en) * 1962-09-06 1965-01-19 Sperry Rand Corp Asynchronous self controlled shift register

Also Published As

Publication number Publication date
FR2210799B1 (fr) 1977-08-12
JPS4983340A (fr) 1974-08-10
GB1452306A (en) 1976-10-13
JPS5710516B2 (fr) 1982-02-26
US3893086A (en) 1975-07-01

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Legal Events

Date Code Title Description
ST Notification of lapse