FR2191270A1 - - Google Patents
Info
- Publication number
- FR2191270A1 FR2191270A1 FR7321783A FR7321783A FR2191270A1 FR 2191270 A1 FR2191270 A1 FR 2191270A1 FR 7321783 A FR7321783 A FR 7321783A FR 7321783 A FR7321783 A FR 7321783A FR 2191270 A1 FR2191270 A1 FR 2191270A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26777172A | 1972-06-30 | 1972-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2191270A1 true FR2191270A1 (de) | 1974-02-01 |
FR2191270B1 FR2191270B1 (de) | 1977-07-29 |
Family
ID=23020055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7321783A Expired FR2191270B1 (de) | 1972-06-30 | 1973-06-06 |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS528229B2 (de) |
CA (1) | CA1005925A (de) |
DE (1) | DE2318912A1 (de) |
FR (1) | FR2191270B1 (de) |
GB (1) | GB1422586A (de) |
IT (1) | IT987426B (de) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2390009A1 (de) * | 1977-05-06 | 1978-12-01 | Siemens Ag | |
EP0078890A2 (de) * | 1981-11-06 | 1983-05-18 | Rockwell International Corporation | Verfahren zur Herstellung einer dielektrisch isolierten CMOS-Halbleiteranordnung mit Isolationsnuten |
EP0082256A2 (de) * | 1981-12-10 | 1983-06-29 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung von Halbleiteranordnungen mit dielektrischen Isolationszonen |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2554450A1 (de) * | 1975-12-03 | 1977-06-16 | Siemens Ag | Verfahren zur herstellung einer integrierten schaltung |
JPS58212165A (ja) * | 1983-05-23 | 1983-12-09 | Nec Corp | 半導体装置 |
JPH0616549B2 (ja) * | 1984-04-17 | 1994-03-02 | 三菱電機株式会社 | 半導体集積回路装置 |
JP2003124514A (ja) * | 2001-10-17 | 2003-04-25 | Sony Corp | 半導体発光素子及びその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1549386A (de) * | 1966-10-05 | 1968-12-13 | ||
FR2079612A5 (de) * | 1970-02-06 | 1971-11-12 | Radiotechnique Compelec | |
FR2080769A1 (de) * | 1970-02-26 | 1971-11-19 | North American Rockwell | |
NL7116712A (de) * | 1970-12-21 | 1972-06-23 | ||
FR2134468A1 (de) * | 1971-04-30 | 1972-12-08 | Standard Microsystems |
-
1973
- 1973-04-14 DE DE2318912A patent/DE2318912A1/de not_active Ceased
- 1973-05-15 IT IT24074/73A patent/IT987426B/it active
- 1973-05-18 JP JP48054847A patent/JPS528229B2/ja not_active Expired
- 1973-06-01 GB GB2620873A patent/GB1422586A/en not_active Expired
- 1973-06-04 CA CA173,051A patent/CA1005925A/en not_active Expired
- 1973-06-06 FR FR7321783A patent/FR2191270B1/fr not_active Expired
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1549386A (de) * | 1966-10-05 | 1968-12-13 | ||
FR2079612A5 (de) * | 1970-02-06 | 1971-11-12 | Radiotechnique Compelec | |
FR2080769A1 (de) * | 1970-02-26 | 1971-11-19 | North American Rockwell | |
NL7116712A (de) * | 1970-12-21 | 1972-06-23 | ||
FR2134468A1 (de) * | 1971-04-30 | 1972-12-08 | Standard Microsystems |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2390009A1 (de) * | 1977-05-06 | 1978-12-01 | Siemens Ag | |
EP0078890A2 (de) * | 1981-11-06 | 1983-05-18 | Rockwell International Corporation | Verfahren zur Herstellung einer dielektrisch isolierten CMOS-Halbleiteranordnung mit Isolationsnuten |
EP0078890A3 (de) * | 1981-11-06 | 1986-05-07 | Rockwell International Corporation | Verfahren zur Herstellung einer dielektrisch isolierten CMOS-Halbleiteranordnung mit Isolationsnuten |
EP0082256A2 (de) * | 1981-12-10 | 1983-06-29 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung von Halbleiteranordnungen mit dielektrischen Isolationszonen |
EP0082256A3 (de) * | 1981-12-10 | 1986-05-07 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung von Halbleiteranordnungen mit dielektrischen Isolationszonen |
Also Published As
Publication number | Publication date |
---|---|
CA1005925A (en) | 1977-02-22 |
JPS528229B2 (de) | 1977-03-08 |
GB1422586A (en) | 1976-01-28 |
IT987426B (it) | 1975-02-20 |
FR2191270B1 (de) | 1977-07-29 |
JPS4945688A (de) | 1974-05-01 |
DE2318912A1 (de) | 1974-01-17 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |