FR2066013A5 - - Google Patents
Info
- Publication number
- FR2066013A5 FR2066013A5 FR7037272A FR7037272A FR2066013A5 FR 2066013 A5 FR2066013 A5 FR 2066013A5 FR 7037272 A FR7037272 A FR 7037272A FR 7037272 A FR7037272 A FR 7037272A FR 2066013 A5 FR2066013 A5 FR 2066013A5
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86655569A | 1969-10-15 | 1969-10-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2066013A5 true FR2066013A5 (enrdf_load_stackoverflow) | 1971-08-06 |
Family
ID=25347860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7037272A Expired FR2066013A5 (enrdf_load_stackoverflow) | 1969-10-15 | 1970-10-15 |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE2049908B2 (enrdf_load_stackoverflow) |
FR (1) | FR2066013A5 (enrdf_load_stackoverflow) |
GB (1) | GB1286737A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2203175A1 (enrdf_load_stackoverflow) * | 1972-10-16 | 1974-05-10 | Matsushita Electric Ind Co Ltd | |
FR2309976A1 (fr) * | 1975-05-01 | 1976-11-26 | Ibm | Procede de fabrication d'un reseau de conducteurs d'interconnexion relativement plan |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3844831A (en) * | 1972-10-27 | 1974-10-29 | Ibm | Forming a compact multilevel interconnection metallurgy system for semi-conductor devices |
US4035276A (en) * | 1976-04-29 | 1977-07-12 | Ibm Corporation | Making coplanar layers of thin films |
DE3228399A1 (de) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer monolithisch integrierten schaltung |
US4561169A (en) * | 1982-07-30 | 1985-12-31 | Hitachi, Ltd. | Method of manufacturing semiconductor device utilizing multilayer mask |
JPS5982746A (ja) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | 半導体装置の電極配線方法 |
US5084414A (en) * | 1985-03-15 | 1992-01-28 | Hewlett-Packard Company | Metal interconnection system with a planar surface |
ATE98814T1 (de) * | 1986-09-30 | 1994-01-15 | Philips Nv | Verfahren zur herstellung einer planarleiterbahn durch isotropes abscheiden von leitendem werkstoff. |
US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
-
1970
- 1970-10-06 GB GB4746270A patent/GB1286737A/en not_active Expired
- 1970-10-10 DE DE19702049908 patent/DE2049908B2/de not_active Ceased
- 1970-10-15 FR FR7037272A patent/FR2066013A5/fr not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2203175A1 (enrdf_load_stackoverflow) * | 1972-10-16 | 1974-05-10 | Matsushita Electric Ind Co Ltd | |
FR2309976A1 (fr) * | 1975-05-01 | 1976-11-26 | Ibm | Procede de fabrication d'un reseau de conducteurs d'interconnexion relativement plan |
Also Published As
Publication number | Publication date |
---|---|
DE2049908A1 (de) | 1971-04-22 |
DE2049908B2 (de) | 1976-03-25 |
GB1286737A (en) | 1972-08-23 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |