FR2029636B1 - - Google Patents

Info

Publication number
FR2029636B1
FR2029636B1 FR7003022A FR7003022A FR2029636B1 FR 2029636 B1 FR2029636 B1 FR 2029636B1 FR 7003022 A FR7003022 A FR 7003022A FR 7003022 A FR7003022 A FR 7003022A FR 2029636 B1 FR2029636 B1 FR 2029636B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7003022A
Other languages
French (fr)
Other versions
FR2029636A1 (enrdf_load_stackoverflow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of FR2029636A1 publication Critical patent/FR2029636A1/fr
Application granted granted Critical
Publication of FR2029636B1 publication Critical patent/FR2029636B1/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
FR7003022A 1969-01-29 1970-01-28 Expired FR2029636B1 (enrdf_load_stackoverflow)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP44005975A JPS4919030B1 (enrdf_load_stackoverflow) 1969-01-29 1969-01-29

Publications (2)

Publication Number Publication Date
FR2029636A1 FR2029636A1 (enrdf_load_stackoverflow) 1970-10-23
FR2029636B1 true FR2029636B1 (enrdf_load_stackoverflow) 1973-10-19

Family

ID=11625834

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7003022A Expired FR2029636B1 (enrdf_load_stackoverflow) 1969-01-29 1970-01-28

Country Status (5)

Country Link
JP (1) JPS4919030B1 (enrdf_load_stackoverflow)
DE (1) DE2003952C3 (enrdf_load_stackoverflow)
FR (1) FR2029636B1 (enrdf_load_stackoverflow)
GB (1) GB1287221A (enrdf_load_stackoverflow)
NL (1) NL142825B (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961353A (en) * 1974-10-21 1976-06-01 International Business Machines Corporation High power semiconductor device
US4016017A (en) * 1975-11-28 1977-04-05 International Business Machines Corporation Integrated circuit isolation structure and method for producing the isolation structure
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit
GB2038548B (en) * 1978-10-27 1983-03-23 Nippon Telegraph & Telephone Isolating semiconductor device by porous silicon oxide

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE671953A (enrdf_load_stackoverflow) * 1964-11-05

Also Published As

Publication number Publication date
DE2003952B2 (de) 1974-08-01
DE2003952C3 (de) 1975-03-20
NL7001170A (enrdf_load_stackoverflow) 1970-07-31
JPS4919030B1 (enrdf_load_stackoverflow) 1974-05-14
NL142825B (nl) 1974-07-15
GB1287221A (en) 1972-08-31
FR2029636A1 (enrdf_load_stackoverflow) 1970-10-23
DE2003952A1 (de) 1972-02-03

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Legal Events

Date Code Title Description
TP Transmission of property